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Machine translation
1. (WO2001037566) METHOD AND APPARATUS FOR DIGITAL SIGNAL PROCESSING
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2001/037566    International Application No.:    PCT/JP2000/008114
Publication Date: 25.05.2001 International Filing Date: 17.11.2000
IPC:
H04N 5/00 (2011.01), H04N 5/44 (2011.01), H04N 7/16 (2011.01), H04N 7/167 (2011.01), H04N 5/46 (2006.01), H04L 9/10 (2006.01)
Applicants: SONY CORPORATION [JP/JP]; 7-35, Kitashinagawa 6-chome, Shinagawa-ku, Tokyo 141-0001 (JP) (For All Designated States Except US).
NAKAMURA, Masashi [JP/JP]; (JP) (For US Only).
MORIWAKI, Hisayoshi [JP/JP]; (JP) (For US Only).
FURUI, Sunao [JP/JP]; (JP) (For US Only).
HAMADA, Ichiro [JP/JP]; (JP) (For US Only)
Inventors: NAKAMURA, Masashi; (JP).
MORIWAKI, Hisayoshi; (JP).
FURUI, Sunao; (JP).
HAMADA, Ichiro; (JP)
Agent: SUGIURA, Masatomo; 7th Floor, Ikebukuro Park Bldg., 49-7, Minami Ikebukuro 2-chome, Toshima-ku, Tokyo 171-0022 (JP)
Priority Data:
11/327162 17.11.1999 JP
Title (EN) METHOD AND APPARATUS FOR DIGITAL SIGNAL PROCESSING
(FR) PROCEDE ET APPAREIL POUR LE TRAITEMENT DE SIGNAUX NUMERIQUES
Abstract: front page image
(EN)Elements required for a digital television receiver are divided into a plurality of digital signal processor blocks and a host microprocessor block. The blocks are connected by general buses, through which commands and streams of data are transferred to control the operations of the blocks. An encryption encoder/decoder circuit is provided on each of the blocks to protect contents transferred through the buses. An encryption encoder/decoder circuit is also provided on an interface with plug-in extension cards so as to protect the contents output from the interface.
(FR)Les éléments nécessaires à un récepteur de télévision numérique sont divisés en plusieurs blocs processeurs de signaux numériques et en un bloc microprocesseur central. Ces blocs sont connectés par des bus généraux, par lesquels les instructions et les flux de données sont transférés pour permettre de commander les opérations de ces blocs. Un circuit codeur/décodeur de cryptage est prévu sur chacun des blocs pour protéger les contenus transférés via ces bus. Un circuit codeur/décodeur de cryptage est également prévu sur une interface avec cartes d'extension enfichables, afin de protéger les contenus extraits de l'interface.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, CA, CH, CN, CR, CU, CZ, DE, DK, DM, DZ, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, TJ, TM, TR, TT, TZ, UA, UG, US, UZ, VN, YU, ZA, ZW.
African Regional Intellectual Property Organization (GH, GM, KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)