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Machine translation
1. (WO2001037334) STRUCTURE AND METHOD FOR DUAL SIDEWALL OXIDATION IN HIGH DENSITY, HIGH PERFORMANCE DRAMS
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2001/037334 International Application No.: PCT/US2000/030400
Publication Date: 25.05.2001 International Filing Date: 02.11.2000
Chapter 2 Demand Filed: 21.05.2001
IPC:
H01L 21/336 (2006.01) ,H01L 21/8242 (2006.01)
Applicants: INFINEON TECHNOLOGIES NORTH AMERICA CORP.[US/US]; 1730 North First Street San Jose, CA 95112-4508, US
INTERNATIONAL BUSINESS MACHINES CORPORATION[US/US]; New Orchard Road Armonk, NY 10504, US
Inventors: BRONNER, Gary, B.; US
DIVAKARUNI, Rama; US
HALLE, Scott; US
RENGARAJAN, Rajesh; US
WEYBRIGHT, Mary, E.; US
MARTIN, Dale, W.; US
Agent: BRADEN, Stanton, C. ; Siemens Corporation - Intellectual Property Dept. 186 Wood Ave. South Iselin, NJ 08830, US
VIGARS, Christopher, Ian; Haseltine Lake & Co. Imperial House 15-19 Kingsway London, WC2B 6UD, US
Priority Data:
09/440,77616.11.1999US
Title (EN) STRUCTURE AND METHOD FOR DUAL SIDEWALL OXIDATION IN HIGH DENSITY, HIGH PERFORMANCE DRAMS
(FR) STRUCTURE ET METHODE POUR OXYDATION DES FLANCS DE GRILLE DE PORTE SUR DES PUCES DRAM HAUTES PERFORMANCES
Abstract: front page image
(EN) This invention relates to integrated circuit product and processes. More particularly, the invention relates to high performance Dynamic Random Access Memory (DRAM) chips and processes for making such chips. An IC fabrication is provided, according to an aspect of the invention, including a silicon wafer, a DRAM array fabrication disposed on said silicon wafer having a first multitude of gate sidewall oxides, and a logic support device fabrication disposed on said wafer adjacent said DRAM array fabrication and having a second multitude of gate sidewall oxides, said first multitude of gate sidewall oxides being substantially thicker than said second multitude of gate sidewall oxides. Methods of making IC fabrications according to the invention are also provided.
(FR) Cette invention concerne ces produits et des procédés qui font intervenir des circuits intégrés. Plus particulièrement, l'invention porte sur des puces RAM dynamiques (DRAM) hautes performances et sur des procédés de fabrication les concernant. Selon l'un de ses aspects, l'invention concerne un circuit imprimé comportant une tranche de silicium, un ensemble DRAM disposé sur ladite couche de silicium et assorti d'une multitude d'oxydes pour paroi de grille de porte et un dispositif de support logique disposé sur ladite tranche, contre l'ensemble DRAM, qui comporte une seconde multitude d'oxydes pour paroi de grille, ladite première multitude d'oxydes pour paroi de grille de porte étant sensiblement plus épaisse que la seconde. L'invention concerne également des procédés de fabrication pour circuits imprimés.
Designated States: JP, KR
European Patent Office (EPO) (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE)
Publication Language: English (EN)
Filing Language: English (EN)