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Machine translation
1. (WO2001037285) METHOD FOR TESTING SEMICONDUCTOR MEMORY
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2001/037285    International Application No.:    PCT/JP1999/006361
Publication Date: 25.05.2001 International Filing Date: 15.11.1999
Chapter 2 Demand Filed:    15.11.1999    
IPC:
G11C 5/06 (2006.01), H01L 23/544 (2006.01)
Applicants: HITACHI, LTD. [JP/JP]; 6, Kanda Surugadai 4-chome Chiyoda-ku Tokyo 101-8010 (JP) (For All Designated States Except US).
HITACHI TOKYO ELECTRONICS CO., LTD. [JP/JP]; 3-2, Fujihashi 3-chome Ome-shi, Tokyo 198-0022 (JP) (For All Designated States Except US).
SATOH, Masayuki [JP/JP]; (JP) (For US Only).
SHIMIZU, Isao [JP/JP]; (JP) (For US Only).
SEITOH, Akira [JP/JP]; (JP) (For US Only).
MIKAMI, Yuji [JP/JP]; (JP) (For US Only).
TAKAHASHI, Masayuki [JP/JP]; (JP) (For US Only).
MOTOYAMA, Yasuhiro [JP/JP]; (JP) (For US Only).
OSHIMA, Takayuki [JP/JP]; (JP) (For US Only).
TAKAGI, Susumu [JP/JP]; (JP) (For US Only)
Inventors: SATOH, Masayuki; (JP).
SHIMIZU, Isao; (JP).
SEITOH, Akira; (JP).
MIKAMI, Yuji; (JP).
TAKAHASHI, Masayuki; (JP).
MOTOYAMA, Yasuhiro; (JP).
OSHIMA, Takayuki; (JP).
TAKAGI, Susumu; (JP)
Agent: OBINATA, Tomio; Yamamoto Building 2F 4, Kagurazaka 3-chome Shinjuku-ku Tokyo 162-0825 (JP)
Priority Data:
Title (EN) METHOD FOR TESTING SEMICONDUCTOR MEMORY
(FR) PROCEDE POUR TESTER DES MEMOIRES A SEMI-CONDUCTEUR
Abstract: front page image
(EN)A variable switch circuit for connecting a wiring for connecting memories together to an arbitrary wiring is provided in a scribe region between memory circuits (chips) formed on a single wafer. An ALPG is constituted of part of the memory circuits. Thus, a test circuit on wafer level for testing the remaining memories by means of such an ALPG is realized.
(FR)Cette invention se rapporte à un circuit de commutation variable, servant à la connexion d'un câblage destiné à connecter des mémoires ensemble à un câblage arbitraire, ce circuit étant placé dans une région de rainurage entre des circuits de mémoire (puces) formés sur une seule plaquette de semi-conducteur. Un ALPG est constitué par une partie de ces circuits de mémoire. On réalise ainsi au niveau de la plaquette un circuit de test servant à tester les mémoires restantes au moyen d'un tel ALPG.
Designated States: CN, JP, KR, SG, US.
European Patent Office (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)