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1. (WO2001035246) CACHE MEMORY SYSTEM AND METHOD FOR A DIGITAL SIGNAL PROCESSOR
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2001/035246 International Application No.: PCT/US2000/030454
Publication Date: 17.05.2001 International Filing Date: 06.11.2000
Chapter 2 Demand Filed: 31.05.2001
IPC:
G06F 13/36 (2006.01) ,G06F 13/38 (2006.01) ,G06F 15/78 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
13
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14
Handling requests for interconnection or transfer
36
for access to common bus or bus system
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
13
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38
Information transfer, e.g. on bus
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
15
Digital computers in general; Data processing equipment in general
76
Architectures of general purpose stored programme computers
78
comprising a single central processing unit
Applicants: ANALOG DEVICES, INC.[US/US]; One Technology Way P.O. Box 9106 Norwood, MA 02062-9106, US
Inventors: KRIVACEK, Paul, D.; US
SOERENSEN, Joern; DK
BOUTAUD, Frederic; US
Agent: ENGELSON, Gary, S.; Wolf, Greenfield & Sacks, P.C. 600 Atlantic Avenue Boston, MA 02210, US
Priority Data:
60/163,81605.11.1999US
Title (EN) CACHE MEMORY SYSTEM AND METHOD FOR A DIGITAL SIGNAL PROCESSOR
(FR) SYSTEME ET PROCEDE DE MEMOIRE CACHE POUR UN PROCESSEUR DE SIGNAUX NUMERIQUES
Abstract:
(EN) A digital signal processing system includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are also plural bus slaves, each connected to its own bus. A bus arbitration module selectively interconnects the buses, so that when the plural bus masters each access a different bus slave, no blocking occurs, and when the plural bus masters each access a same bus slave, bandwidth starvation is avoided. The architecture is supported by a bus arbitration method including hierarchical application of an interrupt-based method, an assigned slot rotation method and a round-robin method, which avoids both bandwidth starvation and lockout during extended periods of bus contention. The system further includes a cache memory system allowing one process to perform real-time digital signal processing according to a modifiable program stored in a modifiable non-volatile memory by temporarily loading portions of the program into a fast, local memory.
(FR) Système de traitement de signaux numériques qui comporte plusieurs processeurs et un ou plusieurs périphériques partagés tels qu'une mémoire. L'architecture comporte plusieurs bus maîtres, chacun étant connecté à son bus propre. Elle comporte également plusieurs bus asservis, chacun étant connecté à son bus propre. Un module d'arbitrage de bus interconnecte sélectivement les bus si bien que quand les bus maîtres accèdent chacun à un bus asservi différent, il n'en résulte pas de blocage, et que quand les bus maîtres accèdent chacun au même bus asservi, l'insuffisance de largeur de bande est évitée. L'architecture est soutenue par un procédé d'arbitrage de bus qui comporte l'application hiérarchique d'un procédé basé sur les interruptions, d'un procédé de rotation des tranches allouées et d'un procédé de permutation circulaire, ce qui permet d'éviter à la fois l'insuffisance de largeur de bande et le verrouillage pendant des périodes prolongées de conflit de bus. Ledit système comporte en outre un système de mémoire cache permettant à un processus d'effectuer le traitement de signaux numériques en temps réel selon un programme modifiable stocké dans une mémoire rémanente modifiable par chargement temporaire de parties du programme dans une mémoire locale rapide.
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, CA, CH, CN, CR, CU, CZ, DE, DK, DM, DZ, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, TJ, TM, TR, TT, TZ, UA, UG, UZ, VN, YU, ZA, ZW
African Regional Intellectual Property Organization (ARIPO) (GH, GM, KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)