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1. (WO2001033628) A METHOD OF FORMING DUAL GATE OXIDE LAYERS OF VARYING THICKNESS ON A SINGLE SUBSTRATE
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2001/033628 International Application No.: PCT/US2000/029468
Publication Date: 10.05.2001 International Filing Date: 26.10.2000
IPC:
H01L 21/762 (2006.01) ,H01L 21/8234 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
76
Making of isolation regions between components
762
Dielectric regions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
Applicants: KONINKLIJKE PHILIPS ELECTRONICS N.V.[NL/NL]; Groenewoudseweg 1 NL-5621 BA Eindhoven, NL
PHILIPS SEMICONDUCTORS, INC.[US/US]; 1000 West Maude Avenue Sunnyvale, CA, US (MC)
Inventors: LUTZE, Jeffrey; US
DE MUIZON, Emmanuel; US
Agent: CRAWFORD, Robert, J.; Crawford PLLC Suite 390 1270 Northland Drive St. Paul, MN 55120, US
Priority Data:
09/432,66602.11.1999US
Title (EN) A METHOD OF FORMING DUAL GATE OXIDE LAYERS OF VARYING THICKNESS ON A SINGLE SUBSTRATE
(FR) PROCEDE DE FABRICATION DE COUCHES D'OXYDE A GRILLE DOUBLE PRESENTANT UNE EPAISSEUR VARIABLE SUR UN SUBSTRAT UNIQUE
Abstract:
(EN) A method for manufacturing a semiconductor device that includes dual gate oxide layers made of two dielectric layers of varying thickness on a single wafer. In an example embodiment, a semiconductor structure is fabricated by providing a first layer of a dielectric over a semiconductor material and covering the first layer with a protective second dielectric layer adapted to mask the first layer. The first and second layers are then removed over a region of the semiconductor material while the second layer is used to protect the first layer, therein leaving the region of semiconductor material substantially exposed. A third layer of dielectric material is formed over the first and second layers and the adjacent exposed semiconductor material region; a gate material is then formed over the third dielectric layer. Finally, an etching step etches through the gate material and underlying layers to the semiconductor material to form a thick gate region and a thin gate region. The thick and thin gate regions can be formed on the same substrate using substantially the same manufacturing process.
(FR) L'invention concerne un procédé de fabrication d'un dispositif semi-conducteur comprenant des couches d'oxyde à grille double fabriquées à partir de deux couches diélectriques d'épaisseur variable sur une tranche unique. Un mode de réalisation consiste à fabriquer une structure de semi-conducteur par application d'une première couche diélectrique sur un matériau semi-conducteur et par recouvrement de la première couche à l'aide d'une deuxième couche diélectrique protectrice conçue pour masquer la première couche. La première couche et la deuxième couche sont ensuite retirées d'une région du matériau semi-conducteur, alors que la deuxième couche est utilisée pour protéger la première couche, laissant ainsi la région du matériau semi-conducteur exposée. Une troisième couche fabriquée à partir d'une matière diélectrique est formée par-dessus les première et deuxième couches et la région du matériau semi-conducteur exposée adjacente. Un matériau barrière est ensuite formé par-dessus la troisième couche diélectrique. Enfin, on procède à la gravure à travers le matériau barrière et les couches sous-jacentes jusqu'au matériau semi-conducteur de manière à former une région barrière épaisse et une région barrière fine. Ces deux régions peuvent être formées sur le même substrat par un procédé sensiblement identique.
front page image
Designated States: CN, JP, KR
European Patent Office (EPO) (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE)
Publication Language: English (EN)
Filing Language: English (EN)