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1. (WO2001031706) METHODS FOR FORMING CO-AXIAL INTERCONNECT LINES IN A CMOS PROCESS

Pub. No.:    WO/2001/031706    International Application No.:    PCT/US2000/024999
Publication Date: Fri May 04 01:59:59 CEST 2001 International Filing Date: Wed Sep 13 01:59:59 CEST 2000
IPC: H01L 21/768
H01L 23/522
Applicants: KONINKLIJKE PHILIPS ELECTRONICS N.V.
PHILIPS SEMICONDUCTORS, INC.
Inventors: BOTHRA, Subhas
GABRIEL, Calvin, Todd
MISHELOFF, Michael
WELING, Milind
Title: METHODS FOR FORMING CO-AXIAL INTERCONNECT LINES IN A CMOS PROCESS
Abstract:
A method for making a semiconductor device with integrated CMOS circuitry and RF circuitry fabricated over a semiconductor wafer, and a semiconductor device with integrated CMOS circuitry and RF circuitry fabricated over a semiconductor wafer is provided. The method includes forming a lower metallization layer and a lower dielectric layer over the lower metallization layer. A metallization line is formed over the lower dielectric layer with an upper dielectric layer over the metallization line. An upper metallization layer is then formed over the upper dielectric layer. After this is completed, oxide spacers are formed along the sides of the lower dielectric layer, the metallization line, and the upper dielectric layer. Finally, an encapsulating metallization layer is formed over the oxide spacers such that the lower metallization layer, the upper metallization layer and the encapsulating metallization layer define an outer shield and the metallization line defines an inner conductor of an RF line.