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1. (WO2001031699) ADVANCED FLIP-CHIP JOIN PACKAGE
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2001/031699 International Application No.: PCT/US2000/026602
Publication Date: 03.05.2001 International Filing Date: 27.09.2000
Chapter 2 Demand Filed: 02.04.2001
IPC:
H01L 21/56 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
56
Encapsulations, e.g. encapsulating layers, coatings
Applicants: INTEL CORPORATION[US/US]; 2200 Mission College Boulevard Santa Clara, CA 95052, US
Inventors: ISHIDA, Kenzo; JP
TAKAHASHI, Kenji; JP
KUBOTA, Jiro; JP
Agent: MALLIE, Michael, J. ; Blakely, Sokoloff, Taylor & Zafman LLP 7th floor 12400 Wilshire Boulevard Los Angeles, CA 90025, US
Priority Data:
09/427,23026.10.1999US
Title (EN) ADVANCED FLIP-CHIP JOIN PACKAGE
(FR) EMBALLAGE POUR FIXATION DE DE RETOURNE AVANCE
Abstract:
(EN) The present invention provides a method of attaching an integrated circuit die to a substrate. The method includes applying solder bumps to contact areas, and placing the inverted integrated circuit die in a desired location such that the solder bumps are in contact with contact areas of the integrated circuit die and the substrate. The solder bumps are heated to mount the die, such that the bumps form a connection between the substrate and the integrated circuit. The gap between the die and the substrate is underfilled by injecting a molding compound into a molding die positioned over the mounted integrated circuit die.
(FR) La présente invention concerne un procédé destiné à fixer un dé de circuit intégré sur un substrat. Ce procédé consiste à appliquer des perles de soudure sur des zones de contact et à placer le dé de circuit intégré inversé dans un endroit désiré de façon que les perles de soudure soient en contact avec les zones de contact du dé de circuit intégré et le substrat. Les perles de soudure sont chauffées pour être montées sur le dé de façon que les perles forment une connexion entre le substrat et le circuit intégré. L'espace entre le dé et le substrat est rempli par injection d'un composé à mouler dans un dé de moulage situé au-dessus du dé de circuit intégré monté.
front page image
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, CA, CH, CN, CR, CU, CZ, DE, DK, DM, DZ, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, TJ, TM, TR, TT, TZ, UA, UG, UZ, VN, YU, ZA, ZW
African Regional Intellectual Property Organization (ARIPO) (GH, GM, KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)