The invention provides a nonvolatile memory circuit that comprises an array of a plurality of cell transistors (M) including a nonconducting trap gate (TG). A plurality of source/drain lines (SDL) are connected commonly to source/drain regions (SD1, SD2) of the cell transistors adjacent in row. The adjacent source and drain lines (SDL) in read voltage state act as bit lines to read data simultaneously during a read cycle of read voltage state (BL), reference voltage state (0V), read voltage state (BL) and floating state (F). These states are created by a page buffer (P/B) connected with the source and drain lines. The page buffer reads and holds data.