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1. (WO2001027930) NONVOLATILE MEMORY FOR STORING MULTIBIT DATA

Pub. No.:    WO/2001/027930    International Application No.:    PCT/JP2000/005573
Publication Date: Apr 19, 2001 International Filing Date: Aug 18, 2000
IPC: G11C 11/56
G11C 16/04
G11C 16/26
Applicants: FUJITSU LIMITED

KAWAMURA, Shoichi

Inventors: KAWAMURA, Shoichi

Title: NONVOLATILE MEMORY FOR STORING MULTIBIT DATA
Abstract:
The invention provides a nonvolatile memory circuit that comprises an array of a plurality of cell transistors (M) including a nonconducting trap gate (TG). A plurality of source/drain lines (SDL) are connected commonly to source/drain regions (SD1, SD2) of the cell transistors adjacent in row. The adjacent source and drain lines (SDL) in read voltage state act as bit lines to read data simultaneously during a read cycle of read voltage state (BL), reference voltage state (0V), read voltage state (BL) and floating state (F). These states are created by a page buffer (P/B) connected with the source and drain lines. The page buffer reads and holds data.