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Machine translation
1. (WO2001024063) METHOD AND APPARATUS FOR DESIGNING SEQUENTIAL CIRCUITS
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2001/024063    International Application No.:    PCT/GB1999/003237
Publication Date: 05.04.2001 International Filing Date: 30.09.1999
Chapter 2 Demand Filed:    27.04.2001    
IPC:
G06F 7/00 (2006.01), G06F 17/50 (2006.01)
Applicants: AUTOMATIC PARALLEL DESIGNS LTD. [GB/GB]; 39 Lyonsdown Road New Barnet Hertfordshire EN5 1LE (GB) (For All Designated States Except US).
TALWAR, Sunil [GB/GB]; (GB) (For US Only)
Inventors: TALWAR, Sunil; (GB)
Agent: COLLINS, John, David; Marks & Clerk 57-60 Lincoln's Inn Fields London WC2A 3LS (GB)
Priority Data:
Title (EN) METHOD AND APPARATUS FOR DESIGNING SEQUENTIAL CIRCUITS
(FR) PROCEDE ET APPAREIL PERMETTANT DE CONCEVOIR DES CIRCUITS SEQUENTIELS
Abstract: front page image
(EN)A method of designing a cascade decomposed sequential circuit is described in which an input state graph for a sequential circuit is used to generate functions defining transitions between states of the sequential circuit. These functions are used to generate sets of states of the sequential circuit and which contain possible states of the sequential circuit. Levels are then assigned to the generated sets and states are assigned to sequential circuit components in accordance with the assigned levels. These assigned states comprise the current states of the sequential circuit components and using these states and the functions, next states for these sequential circuit components are derived.
(FR)La présente invention concerne un procédé permettant de concevoir un circuit séquentiel à décomposition en cascade dans lequel on utilise un graphe d'état d'entrée de circuit séquentiel pour générer des fonctions définissant des transitions entre les états du circuit séquentiel. On utilise ces fonctions pour produire des ensembles d'états de circuit séquentiel, qui contiennent les états possibles du circuit séquentiel. On attribue ensuite des niveaux aux ensembles produits et on attribue des états aux composants de circuit séquentiel conformément aux niveaux attribués. Les états attribués comprennent les états en cours des composants du circuit séquentiel, et on dérive les états suivants des composants du circuit séquentiel au moyen des états et fonctions précités.
Designated States: AE, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, CA, CH, CN, CR, CU, CZ, DE, DK, DM, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MD, MG, MK, MN, MW, MX, NO, NZ, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, TJ, TM, TR, TT, TZ, UA, UG, US, UZ, VN, YU, ZA, ZW.
African Regional Intellectual Property Organization (GH, GM, KE, LS, MW, SD, SL, SZ, TZ, UG, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)