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1. WO2001015361 - ROUTING INTERFACES INTO A BACKPLANE

Publication Number WO/2001/015361
Publication Date 01.03.2001
International Application No. PCT/FI2000/000697
International Filing Date 17.08.2000
Chapter 2 Demand Filed 12.02.2001
IPC
H04J 3/04 2006.1
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
JMULTIPLEX COMMUNICATION
3Time-division multiplex systems
02Details
04Distributors combined with modulators or demodulators
H04J 3/16 2006.1
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
JMULTIPLEX COMMUNICATION
3Time-division multiplex systems
16in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
H04Q 11/04 2006.1
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
QSELECTING
11Selecting arrangements for multiplex systems
04for time-division multiplexing
CPC
H04J 3/047
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
JMULTIPLEX COMMUNICATION
3Time-division multiplex systems
02Details
04Distributors combined with modulators or demodulators
047Distributors with transistors or integrated circuits
H04J 3/1611
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
JMULTIPLEX COMMUNICATION
3Time-division multiplex systems
16in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
1605Fixed allocated frame structures
1611Synchronous digital hierarchy [SDH] or SONET
H04J 3/1641
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
JMULTIPLEX COMMUNICATION
3Time-division multiplex systems
16in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
1605Fixed allocated frame structures
1623Plesiochronous digital hierarchy [PDH]
1641Hierarchical systems
H04Q 11/04
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
QSELECTING
11Selecting arrangements for multiplex systems
04for time-division multiplexing
H04Q 2213/13003
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
QSELECTING
2213Indexing scheme relating to selecting arrangements in general and for multiplex systems
13003Constructional details of switching devices
H04Q 2213/13076
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
QSELECTING
2213Indexing scheme relating to selecting arrangements in general and for multiplex systems
13076Distributing frame, MDF, cross-connect switch
Applicants
  • NOKIA NETWORKS OY [FI]/[FI] (AllExceptUS)
  • LAUMANN, Jorg [DE]/[DE] (UsOnly)
Inventors
  • LAUMANN, Jorg
Agents
  • KOLSTER OY AB
Priority Data
PQ 234019.08.1999AU
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) ROUTING INTERFACES INTO A BACKPLANE
(FR) INTERFACES D'ACHEMINEMENT EN FONDS DE PANIER
Abstract
(EN) A method and data interface unit for routing two or more data input streams into one or more data output streams is disclosed. A Data Interface Unit (20) has two input modules (30,32), providing four interface input channels (40-46). A logical AND gate (70) receives four input TDM buses; and outputs on two output TDM buses to a bus interface ASIC (80). Two or four TDM buses can be switched to a respective TDM output bus. For two such buses, this is done in a manner such that a first data block from a frame of an input stream is mapped to the beginning part of an output stream, and a second data block from a frame of another input stream is mapped to the end part of an output stream.
(FR) La présente invention concerne un procédé et une unité d'interface de données destinés à acheminer deux ou plusieurs flux d'entrée de données en un ou plusieurs flux de sortie de données. Une unité d'interface de données (20) comporte deux modules d'entrée (30,32), offrant quatre canaux d'entrée d'interface (40-46). Une porte logique ET (70) reçoit quatre bus d'entrée à multiplexage temporel et comporte à sa sortie deux bus de sortie à multiplexage temporel menant à une interface de bus à circuit intégré spécifique (ASIC) (80). Il est possible de commuter deux des quatre bus à multiplexage temporel respectivement en un bus de sortie à multiplexage temporel. Pour deux tels bus, cette opération est effectuée de telle manière qu'un premier bloc de données d'une trame d'un flux d'entrée soit appliqué sur la partie initiale d'un flux de sortie, et qu'un second bloc de données d'une trame d'un autre flux d'entrée soit appliqué sur la partie terminale d'un flux de sortie.
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