The present invention relates to communication of data between two parties in a multi master bus system, like PCI bus or VME bus, using shared RAM. The parties may comprise two CPUs, two SW processes executing on the same processor, or a SW process and an interrupt routine. In said RAM there is arranged a FIFO memory locally to each party. Each part may read from its local FIFO memory and write to the other party's FIFO memory only. In this way only write operations are performed on the bus.