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1. (WO2001005089) SECURITY CHIP ARCHITECTURE AND IMPLEMENTATIONS FOR CRYPTOGRAPHY ACCELERATION
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2001/005089 International Application No.: PCT/US2000/018545
Publication Date: 18.01.2001 International Filing Date: 07.07.2000
Chapter 2 Demand Filed: 07.02.2001
IPC:
G06F 1/00 (2006.01) ,G06F 9/38 (2006.01) ,G06F 21/00 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
1
Details not covered by groups G06F3/-G06F13/82
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
30
Arrangements for executing machine- instructions, e.g. instruction decode
38
Concurrent instruction execution, e.g. pipeline, look ahead
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
21
Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
Applicants: KRISHNA, Suresh[US/US]; US (UsOnly)
OWEN, Christopher[US/US]; US (UsOnly)
BROADCOM CORPORATION[US/US]; 16215 Alton Parkway Irvine, CA 92618, US (AllExceptUS)
Inventors: KRISHNA, Suresh; US
OWEN, Christopher; US
Agent: AUSTIN, James, E.; Beyer Weaver & Thomas, LLP P.O. Box 130 Mountain View, CA 94042-0130, US
Priority Data:
09/510,48623.02.2000US
60/142,87008.07.1999US
60/159,01212.10.1999US
Title (EN) SECURITY CHIP ARCHITECTURE AND IMPLEMENTATIONS FOR CRYPTOGRAPHY ACCELERATION
(FR) ARCHITECTURE DE PUCE DE SECURITE ET REALISATION D'UNE ACCELERATION CRYPTOGRAPHIQUE
Abstract:
(EN) An architecture and a method for a cryptography acceleration is disclosed that allows significant performance improvements without the use of external memory. Specifically, the chip architecture enables 'cell-based' processing of random-length IP packets. The IP packets, which may be of variable and unknown size, are split into fixed-size 'cells'. The fixed-sized cells are then processed and reassembled into packets. The cell-based packet processing architecture of the present invention allows the implementation of a processing pipeline that has known processing throughput and timing characteristics, thus making it possible to fetch and process the cells in a predictable time frame. The architecture is scalable and is also independent of the type of cryptography performed. The cells may be fetched ahead of time (pre-fetched) and the pipeline may be staged in such a manner that attached (local) memory is not required to store packet data or control parameters.
(FR) L'invention concerne une architecture et un procédé d'accélération cryptographique, permettant d'améliorer considérablement les performances sans recourir à une mémoire extérieure. Plus spécifiquement, l'architecture de puce permet d'effectuer un traitement « sur la base de cellules » de paquets IP de longueur aléatoire. Les paquets IP, qui peuvent être de taille variable et inconnue, sont divisés en « cellules » de taille fixe. Les cellules de taille fixe sont ensuite soumises à un traitement, puis rassemblées en paquets. L'architecture de traitement de paquets sur la base de cellules selon la présente invention permet d'installer un pipeline de traitement possédant des caractéristiques de vitesse de traitement et de synchronisation connues, ce qui facilite l'extraction et le traitement des cellules dans une base de temps prévisible. L'architecture est échelonnable et est indépendant du type de cryptographie effectué. Les cellules peuvent être extraites à l'avance (pré-extraites) et le pipeline peut comporter des degrés, de sorte qu'une mémoire jointe (locale) ne soit pas nécessaire pour mémoriser des données en paquets ou des paramètres de commande.
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, CA, CH, CN, CR, CU, CZ, DE, DK, DM, DZ, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, TJ, TM, TR, TT, TZ, UA, UG, US, UZ, VN, YU, ZA, ZW
African Regional Intellectual Property Organization (ARIPO) (GH, GM, KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)