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1. (WO2001003190) SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2001/003190 International Application No.: PCT/JP1999/003523
Publication Date: 11.01.2001 International Filing Date: 30.06.1999
Chapter 2 Demand Filed: 30.06.1999
IPC:
G11C 11/405 (2006.01) ,H01L 27/108 (2006.01)
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
11
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21
using electric elements
34
using semiconductor devices
40
using transistors
401
forming cells needing refreshing or charge regeneration, i.e. dynamic cells
403
with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
405
with three charge-transfer gates, e.g. MOS transistors, per cell
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
108
Dynamic random access memory structures
Applicants: SYUKURI, Syoji[JP/JP]; JP (UsOnly)
SAKATA, Takeshi[JP/JP]; JP (UsOnly)
HITACHI, LTD.[JP/JP]; 6, Kanda Surugadai 4-chome Chiyoda-ku Tokyo 101-8010, JP (AT, BE, CH, CN, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, JP, KR, LU, MC, NL, PT, SE, SG)
Inventors: SYUKURI, Syoji; JP
SAKATA, Takeshi; JP
Agent: TOKUWAKA, Kousei; 16-8, Inokashira 5-Chome Mitaka-Shi Tokyo 181-0001, JP
Priority Data:
Title (EN) SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
(FR) CIRCUIT INTEGRE A SEMI-CONDUCTEURS
Abstract:
(EN) At the intersections of bit lines and first and second word lines for reading and writing respectively, for a storage capacitor for storing information charge, a memory cell is provided, which comprises a read switching MOSFET having a gate connected to the first word line and source-drains one of which is connected to a storage node of the storage capacitor, a write switching MOSFET having a gate connected to the second word line and a source-drain path connected to the bit lines and the storage node of the storage capacitor, and an amplifying transistor having a collector formed in the semiconductor region where the read switching MOSFET is formed, a base which is the other source-drain of the read switching MOSFET, and an emitter formed in the base region and connected to the bit lines.
(FR) A l'intersection des canaux bits et des premiers et deuxièmes canaux mots d'un condensateur de stockage de charges d'information, servant respectivement à la lecture et à l'écriture, on dispose une cellule de mémoire comportant un MOSFET commutateur de lecture présentant une porte reliée au premier canal mot et aux sources-drains dont l'un est relié à un noeud de stockage du condensateur de stockage. Un MOSFET commutateur dont une porte est reliée au deuxième canal mot et une liaison source-drain reliée aux canaux mots et aux noeuds de stockage du condensateur de stockage, et un transistor amplificateur dont le collecteur est formé sur la zone semi-conductrice où est formé le MOSFET commutateur de lecture, une base constituant l'autre source-drain du MOSFET commutateur de lecture, et un émetteur formé dans la région de base et relié aux lignes de bits.
front page image
Designated States: CN, JP, KR, SG, US
European Patent Office (EPO) (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)