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Machine translation
1. (WO2001001576) A LOW POWER MULTIPLEXER WITH SHARED, CLOCKED TRANSISTOR
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2001/001576    International Application No.:    PCT/US2000/040109
Publication Date: 04.01.2001 International Filing Date: 05.06.2000
Chapter 2 Demand Filed:    21.12.2000    
IPC:
H03K 17/693 (2006.01), H03K 19/173 (2006.01)
Applicants: INTEL CORPORATION [US/US]; 2200 Mission College Boulevard, Santa Clara, CA 95052 (US) (For All Designated States Except US).
LAN, Jiann-Cherng, James [US/US]; (US) (For US Only).
NEMANI, Mahadevamurty [IN/US]; (US) (For US Only).
VIJAYRAO, Narsing, K. [IN/US]; (US) (For US Only).
JIANG, Wenjie [CN/US]; (US) (For US Only).
KUMAR, Sudarshan [IN/US]; (US) (For US Only)
Inventors: LAN, Jiann-Cherng, James; (US).
NEMANI, Mahadevamurty; (US).
VIJAYRAO, Narsing, K.; (US).
JIANG, Wenjie; (US).
KUMAR, Sudarshan; (US)
Agent: MALLIE, Michael, J.; Blakely, Sokoloff, Taylor & Zafman LLP, 7th floor, 12400 Wilshire Boulevard, Los Angeles, CA 90025 (US)
Priority Data:
09/343,961 30.06.1999 US
Title (EN) A LOW POWER MULTIPLEXER WITH SHARED, CLOCKED TRANSISTOR
(FR) MULTIPLEXEUR A FAIBLE PUISSANCE MUNI D'UN TRANSISTOR PARTAGE CADENCE
Abstract: front page image
(EN)A circuit includes first and second pull-up transistors (301, 302) having first and second drains, respectively, each coupled to separate voltage clamps (310, 311). The gates of each of the two pull-up transistors are coupled to a clock signal line. The circuit further includes a shared pull-down transistor (305), the gate of which is coupled to the clock signal line. The drain of the shared pull-down transistor (305) is coupled to the first drain via at least one pull-down transistor (303, 363, 304, 364) ) in series with the shared pull-down transistor. The drain of the shared pull-down transistor is also coupled to the second drain via at least one pull-down transistor (305) in series with the shared pull-down transistor (303, 363, 304, 364). This circuit may be found useful in multiplexing applications.
(FR)La présente invention concerne un circuit comprenant un premier (301) et un second (302) transistor à excursion haute cadencés comprenant, respectivement, un premier et un second drain, couplé chacun à des dispositifs de blocage de tension séparés (310, 311). Les grilles de chacun des deux transistors d'excursion haute sont couplés à une ligne de signaux d'horloge. Le circuit comprend en outre un transistor partagé d'excursion basse (305) dont la grille est couplée à la ligne de signaux d'horloge. Le drain du transistor d'excursion basse partagé est couplé au premier drain via au moins un transistor d'excursion basse (303, 363, 304, 364) en série avec le transistor partagé d'excursion basse (305). Le drain du transistor partagé d'excursion basse (305) est également couplé au second drain via au moins un transistor d'excursion basse (303, 363, 304, 364) en série avec le transistor d'excursion basse partagé. Le circuit de l'invention peut être utilisé dans les applications de multiplexage.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, CA, CH, CN, CR, CU, CZ, DE, DK, DM, DZ, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, TJ, TM, TR, TT, TZ, UA, UG, US, UZ, VN, YU, ZA, ZW.
African Regional Intellectual Property Organization (GH, GM, KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)