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1. (WO2000062470) UNIVERSAL SYNCHRONOUS NETWORK SYSTEM FOR INTERNET PROCESSOR AND WEB OPERATING ENVIRONMENT
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2000/062470    International Application No.:    PCT/US2000/010101
Publication Date: 19.10.2000 International Filing Date: 14.04.2000
Chapter 2 Demand Filed:    06.11.2000    
IPC:
H04J 3/06 (2006.01), H04L 7/00 (2006.01), H04L 25/03 (2006.01)
Applicants: SAPHIRE COMMUNICATIONS, INC. [US/US]; 2390 Walsh Avenue, Santa Clara, CA 95051 (US)
Inventors: TRANS, Francois; (US)
Agent: MCNELIS, John, T.; Fenwick & West LLP, Two Palo Alto Square, Palo Alto, CA 94306 (US)
Priority Data:
60/129,314 14.04.1999 US
09/417,528 13.10.1999 US
09/444,007 19.11.1999 US
60/170,455 13.12.1999 US
PCT/US00/06842 15.03.2000 US
Title (EN) UNIVERSAL SYNCHRONOUS NETWORK SYSTEM FOR INTERNET PROCESSOR AND WEB OPERATING ENVIRONMENT
(FR) SYSTEME DE RESEAU SYNCHRONE UNIVERSEL POUR PROCESSEUR INTERNET ET ENVIRONNEMENT DE FONCTIONNEMENT INTERNET
Abstract: front page image
(EN)A method for increasing bandwidth of signals between a transmitting and receiving nodes is provided. A time synchronization signal is received. Clock tuning logic (161) synchronizes the transmitting and receiving nodes using the received synchronization signal. Channel measurement logic (164) measures the capacity of the communication channel. Channel calibration logic (163) calibrates the communications channel using the capacity measurements. Precision sampling logic (165) samples the clock signal of the nodes. Phase adjustement is delivered to the nodes when a sampled clock signal exceeds a phase interval.
(FR)Cette invention concerne un procédé permettant d'augmenter la largeur de bande des signaux entre des noeuds d'émission et de réception. Sur réception d'un signal de synchronisation, une logique de réglage fin d'horloge (161) synchronise les noeuds d'émission et de réception au moyen dudit signal. Une logique de mesure de canal (164) mesure la capacité du canal de communication. Une logique d'étalonnage (163) étalonne le canal de communication sur la base de relevés de capacité. Une logique d'échantillonnage de précision (165) échantillonne le signal d'horloge des noeuds. Un ajustement de phase est transmis aux noeuds lorsque un signal d'horloge échantillonné dépasse l'intervalle phase.
Designated States: AE, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, CA, CH, CN, CU, CZ, DE, DK, EE, ES, FI, GB, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MD, MG, MK, MN, MW, MX, NO, NZ, PL, PT, RO, RU, SD, SE, SG, SI, SK, TJ, TM, TR, TT, UA, UG, UZ, VN, YU, ZA, ZW.
African Regional Intellectual Property Organization (GH, GM, KE, LS, MW, SD, SL, SZ, TZ, UG, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)