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Machine translation
1. (WO2000059033) WIRING BOARD, CONNECTION BOARD, SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURE THEREOF, CIRCUIT BOARD, AND ELECTRONIC DEVICE
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2000/059033    International Application No.:    PCT/JP2000/001769
Publication Date: 05.10.2000 International Filing Date: 23.03.2000
IPC:
H01L 21/48 (2006.01), H01L 23/498 (2006.01), H05K 3/36 (2006.01), H05K 3/40 (2006.01)
Applicants: SEIKO EPSON CORPORATION [JP/JP]; 4-1, Nishi-shinjuku 2-chome, Shinjuku-ku, Tokyo 163-0811 (JP) (For All Designated States Except US).
HASHIMOTO, Nobuaki [JP/JP]; (JP) (For US Only)
Inventors: HASHIMOTO, Nobuaki; (JP)
Agent: INOUE, Hajime; Ogikubo TM Building, 2nd Floor 26-13, Ogikubo 5-chome, Suginami-ku, Tokyo 167-0051 (JP)
Priority Data:
11/81028 25.03.1999 JP
11/213183 28.07.1999 JP
Title (EN) WIRING BOARD, CONNECTION BOARD, SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURE THEREOF, CIRCUIT BOARD, AND ELECTRONIC DEVICE
(FR) TABLEAU DE REPARTITION, TABLEAU DE CONNEXION, DISPOSITIF SEMI-CONDUCTEUR, SON PROCEDE DE FABRICATION, CARTE DE CIRCUIT IMPRIME, ET INSTRUMENT ELECTRONIQUE
Abstract: front page image
(EN)A circuit board comprises a substrate (10) with holes (14), a wiring pattern (20) formed on one side of the substrate (10) and including bumps (22) projecting through the holes (14) beyond the other side of the substrate (10), and resin filling (26) inside the bumps (22), which allows the bumps to deform to a limited extent. The bumps (22) serve as external terminals of a semiconductor device.
(FR)La présente invention concerne une carte de circuit imprimé comportant un substrat (10) présentant des perçages (14), un motif de fils (20) formé sur un côté du substrat (10) et comprenant des bosses (22) en saillie à travers les perçages (14) au delà de l'autre côté du substrat (10), et une charge de résine (26) à l'intérieur des bosses (22), permettant aux bosses de se déformer de manière limitée. Les bosses (22) agissent en tant que bornes extérieures du dispositif semi-conducteur.
Designated States: CN, JP, KR, US.
European Patent Office (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)