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1. WO2000044209 - SYSTEM AND METHOD FOR INTERCONNECTING LAYERS IN A PRINTED CIRCUIT BOARD

Publication Number WO/2000/044209
Publication Date 27.07.2000
International Application No. PCT/US2000/001518
International Filing Date 21.01.2000
Chapter 2 Demand Filed 27.07.2000
IPC
H05K 1/11 2006.01
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1Printed circuits
02Details
11Printed elements for providing electric connections to or between printed circuits
H05K 3/46 2006.01
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3Apparatus or processes for manufacturing printed circuits
46Manufacturing multi-layer circuits
CPC
H05K 1/112
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1Printed circuits
02Details
11Printed elements for providing electric connections to or between printed circuits
111Pads for surface mounting, e.g. lay-out
112directly combined with via connections
H05K 2201/09227
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
2201Indexing scheme relating to printed circuits covered by H05K1/00
09Shape and layout
09209Shape and layout details of conductors
09218Conductive traces
09227Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
H05K 2201/09327
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
2201Indexing scheme relating to printed circuits covered by H05K1/00
09Shape and layout
09209Shape and layout details of conductors
0929Conductive planes
09327Special sequence of power, ground and signal layers in multilayer PCB
H05K 2201/10734
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
2201Indexing scheme relating to printed circuits covered by H05K1/00
10Details of components or other objects attached to or integrated in a printed circuit board
10613Details of electrical connections of non-printed components, e.g. special leads
10621Components characterised by their electrical contacts
10734Ball grid array [BGA]; Bump grid array
H05K 2203/1572
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
2203Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
15Position of the PCB during processing
1572Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
H05K 3/4644
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3Apparatus or processes for manufacturing printed circuits
46Manufacturing multilayer circuits
4644by building the multilayer layer by layer, i.e. build-up multilayer circuits
Applicants
  • INTERWORKS COMPUTER PRODUCTS, INC. [US/US]; 103 North Pointe Drive Lake Forest, CA 92630, US
Inventors
  • KOONTZ, Jerry, D.; US
Agents
  • ALTMAN, Daniel, E.; Knobbe, Martens, Olson and Bear, LLP 620 Newport Center Drive 16th Floor Newport Beach, CA 92660, US
Priority Data
09/235,97022.01.1999US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) SYSTEM AND METHOD FOR INTERCONNECTING LAYERS IN A PRINTED CIRCUIT BOARD
(FR) CONNEXIONS INTERCOUCHE DANS UNE CARTE A CIRCUITS IMPRIMES ET SYSTEME A CET EFFET
Abstract
(EN)
A printed circuit module (50) supports host processors and memories. The module permits easy upgrades and repairs of the semiconductor devices without requiring modification of the motherboard. The module (50) includes a multilayer printed circuit board with a symmetrical design, permitting integrated circuits to be placed on both sides of the board. Microvias (170) connect the contact points on a signal layer (88, 124) directly to a ground layer (92, 120) on the printed circuit board, thereby reducing the need for escape routing. This greatly simplifies the design layout of the module (50). The ground layer (92) is located between two signal layers (88, 96), thereby decreasing the crosstalk between the signal layers. The symmetrical design permits drilled vias (160) to extend from a quadrant of one integrated circuit and exit through a similar quadrant on the opposite side of the circuit board. The modular design also simplifies impedance matching. Testing of the module (50) may also be accomplished even when the module is not fully populated through the use of test bypass circuitry.
(FR)
Un module circuit imprimé (50) permet le fonctionnement de processeurs hôtes et de mémoires. Ce module facilite les mises à niveau et les réparations des dispositifs à semi-conducteurs sans qu'il y ait besoin de modifier la carte mère. Le module (50) comporte une carte à circuits imprimés multicouche symétrique permettant de monter les circuits intégrés sur les deux faces de la cartes. Des micropassages de contact (170) connectent les points de contact d'une couche de signal (88, 124) directement à une couche de base (92, 120) de la carte à circuits imprimés, ce qui permet de se dispenser des tracés de fuite. Cela vient faciliter grandement l'implantation du module (50) dans le plan. La couche de base (92) est située entre deux couches de signal (86, 96), ce qui diminue la diaphonie entre couches de signal. Cette structure symétrique permet d'avoir des passages de contact percés (160) allant d'un secteur d'un premier circuit intégré et ressortant par un secteur similaire sur la face opposée de la carte à circuits intégrés. La structure modulaire facilite également les accords d'impédances. Les tests du module (50) peuvent également se faire alors que le module n'est pas entièrement occupé, et ce, grâce à l'utilisation d'un circuit de dérivation de test.
Also published as
Latest bibliographic data on file with the International Bureau