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1. WO2000044095 - FPGA INTEGRATED CIRCUIT HAVING EMBEDDED SRAM MEMORY BLOCKS AND INTERCONNECT CHANNEL FOR BROADCASTING ADDRESS AND CONTROL SIGNALS

Publication Number WO/2000/044095
Publication Date 27.07.2000
International Application No. PCT/US2000/001482
International Filing Date 20.01.2000
IPC
H03K 19/177 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
02using specified components
173using elementary logic circuits as components
177arranged in matrix form
CPC
H03K 19/17736
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
02using specified components
173using elementary logic circuits as components
177arranged in matrix form
17736Structural details of routing resources
H03K 19/1776
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
02using specified components
173using elementary logic circuits as components
177arranged in matrix form
17748Structural details of configuration resources
1776for memories
Applicants
  • LATTICE SEMICONDUCTOR CORPORATION [US/US]; 995 Stewart Drive Sunnyvale, CA 94088, US
Inventors
  • AGRAWAL, Om, P.; US
  • CHANG, Herman, M.; US
  • SHARPE-GEISLER, Bradley, A.; US
  • NGUYEN, Bai; US
Agents
  • FLIESLER, Martin, C. ; Fliesler, Dubb, Meyer and Lovejoy LLP Suite 400 Four Embarcadero Center San Francisco, CA 94111-4156, US
Priority Data
09/235,35121.01.1999US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) FPGA INTEGRATED CIRCUIT HAVING EMBEDDED SRAM MEMORY BLOCKS AND INTERCONNECT CHANNEL FOR BROADCASTING ADDRESS AND CONTROL SIGNALS
(FR) CIRCUIT INTEGRE PREDIFFUSE PROGRAMMABLE COMPORTANT DES BLOCS MEMOIRE SRAM INCLUS ET UN CANAL D'INTERCONNEXION PERMETTANT DE DIFFUSER LES SIGNAUX D'ADRESSE ET DE COMMANDE
Abstract
(EN)
A field-programmable gate array device (FPGA) having plural rows and columns of logic function units (VGB's) further includes a plurality of embedded memory blocks, where each memory block is embedded in a corresponding row of logic function units. Each embedded memory block has an address port for capturing received address signals and a controls port for capturing supplied control signals. Interconnect resources are provided including a Memory Controls-conveying Interconnect Channel (MCIC) for conveying shared address and control signals to plural ones of the memory blocks on a broadcast or narrowcast basis.
(FR)
Dispositif circuit intégré prédiffusé programmable (FPGA), qui comprend plusieurs lignes et colonnes d'unités fonctionnelles logiques (VGB) et qui comporte une pluralité de blocs mémoire inclus, chaque bloc mémoire étant inclus dans la ligne correspondante des unités fonctionnelles logiques. Chaque bloc mémoire inclus comporte un port d'adresses qui permet de recevoir les signaux d'adresse et un port de commandes qui permet d'émettre les signaux de commande. Le dispositif comporte également des ressources d'interconnexion, notamment un canal d'interconnexion de transport des commandes mémoire (MCIC), qui amène les signaux d'adresse et de mémoire partagés à plusieurs blocs mémoire sur la base d'une diffusion bande large ou d'une diffusion ciblée.
Also published as
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