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1. WO2000044089 - GATE BIASING ARRANGEMENT

Publication Number WO/2000/044089
Publication Date 27.07.2000
International Application No. PCT/SE1999/002504
International Filing Date 30.12.1999
Chapter 2 Demand Filed 18.08.2000
IPC
H03F 1/30 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
FAMPLIFIERS
1Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
30Modifications of amplifiers to reduce influence of variations of temperature or supply voltage
CPC
H03F 1/301
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
FAMPLIFIERS
1Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
30Modifications of amplifiers to reduce influence of variations of temperature or supply voltage ; or other physical parameters
301in MOSFET amplifiers
H03F 2200/18
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
FAMPLIFIERS
2200Indexing scheme relating to amplifiers
18the bias of the gate of a FET being controlled by a control signal
Applicants
  • TELEFONAKTIEBOLAGET LM ERICSSON (publ) [SE/SE]; S-126 25 Stockholm, SE
Inventors
  • ERICSSON, Per; SE
  • AFEKENSTAM, Nils; SE
  • JOHANSSON, Jan; SE
  • SJÖDEN, Henrik; US
Agents
  • ERICSSON MICROELECTRONICS AB; Department for Intellectual Property Rights S-164 81 Kista-Stockholm, SE
Priority Data
9900210-725.01.1999SE
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) GATE BIASING ARRANGEMENT
(FR) ENSEMBLE POLARISATION DE LA GRILLE
Abstract
(EN)
To eliminate the temperature dependency of the quiescent current of a power transistor (1), the gate bias voltage of the power transistor (1) is controlled by means of the output voltage of a biasing transistor (3) residing on the same silicon chip as the power transistor (1), and by interconnecting the gate (G3) and drain (D3) of the biasing transistor (3) and feeding it with a constant current (IB) from external circuitry.
(FR)
Afin d'éliminer la sensibilité à la température du courant de repos d'un transistor de puissance (1), on régule la tension de polarisation de la grille de ce transistor de puissance (1) à l'aide de la tension de sortie d'un transistor de polarisation (3), placé sur la même puce de silicium que ledit transistor de puissance (1), et on interconnecte la grille (G3) et le drain (D3) dudit transistor de polarisation (3) tout en fournissant à ce dernier un courant constant (IB) depuis des circuits extérieurs.
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