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1. WO2000044044 - METHOD FOR REDUCING THE CAPACITANCE BETWEEN INTERCONNECTS BY FORMING VOIDS IN DIELECTRIC MATERIAL

Publication Number WO/2000/044044
Publication Date 27.07.2000
International Application No. PCT/US2000/001429
International Filing Date 20.01.2000
IPC
H01L 21/768 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71Manufacture of specific parts of devices defined in group H01L21/7086
768Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
CPC
H01L 21/7682
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76801characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
7682the dielectric comprising air gaps
H01L 23/5222
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another ; , i.e. interconnections, e.g. wires, lead frames
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
5222Capacitive arrangements or effects of, or between wiring layers
H01L 2924/0002
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2924Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
0001Technical content checked by a classifier
0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Applicants
  • KONINKLIJKE PHILIPS ELECTRONICS N.V. [NL/NL]; Groenewoudseweg 1 5621 BA Eindhoven, NL
Inventors
  • BOTHRA, Subhas; US
  • ANNAPRAGADA, Rao; US
Priority Data
09/234,29220.01.1999US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) METHOD FOR REDUCING THE CAPACITANCE BETWEEN INTERCONNECTS BY FORMING VOIDS IN DIELECTRIC MATERIAL
(FR) PROCEDE DE REDUCTION DE LA CAPACITANCE ENTRE DES INTERCONNEXIONS EN FORMANT DES VIDES DANS LE MATERIAU DIELECTRIQUE
Abstract
(EN)
A method of manufacturing semiconductors is provided which avoids metal deposition in voids [216] formed in the dielectric [210] between interconnects [206, 208]. In a preferred embodiment, an etch stop recess portion [220] is provided over the dielectric [210] which encloses the interconnects [206, 208] to prevent via openings [224, 226] from extending into the voids [216] during the etching of the via openings [224, 226]. Accordingly, metal deposition of the voids [216] during metal deposition of the vias [224, 226] is avoided. As a result, the semiconductors so formed have reduced capacitance between the interconnects [206, 208] and improved reliability since the voids [216] are cleared of any metal deposition.
(FR)
La présente invention concerne un procédé de fabrication de semiconducteurs empêchant la formation de dépôts métalliques dans les vides (216) formés dans le diélectrique (210), entre les connexions (206, 208). Dans un mode de réalisation préféré, un évidement d'arrêt d'attaque (220) est ménagé sur le diélectrique (210) comprenant les interconnexions (206, 208) pour empêcher les passages (224, 226) de s'étendre dans les vides (216) lors de l'attaque de ces passages (224, 226). De même, on empêche la formation de dépôt métallique dans les vides (216) lors du dépôt métallique des passages (224, 226). Par conséquent, les semiconducteurs ainsi formés présentent une capacitance réduite entre les interconnexions (206, 208) et une meilleure performance, étant donnée que les vides (216) sont débarrassés de tout dépôt métallique.
Also published as
Latest bibliographic data on file with the International Bureau