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1. WO2000044043 - SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Publication Number WO/2000/044043
Publication Date 27.07.2000
International Application No. PCT/JP1999/000253
International Filing Date 22.01.1999
Chapter 2 Demand Filed 22.01.1999
IPC
H01L 21/60 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H01L 21/768 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71Manufacture of specific parts of devices defined in group H01L21/7086
768Applying interconnections to be used for carrying current between separate components within a device
CPC
H01L 21/76843
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76838characterised by the formation and the after-treatment of the conductors
76841Barrier, adhesion or liner layers
76843formed in openings in a dielectric
H01L 21/7685
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76838characterised by the formation and the after-treatment of the conductors
76841Barrier, adhesion or liner layers
7685the layer covering a conductive structure
H01L 21/76852
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76838characterised by the formation and the after-treatment of the conductors
76841Barrier, adhesion or liner layers
7685the layer covering a conductive structure
76852the layer also covering the sidewalls of the conductive structure
H01L 21/76873
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76838characterised by the formation and the after-treatment of the conductors
76841Barrier, adhesion or liner layers
76871Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
76873for electroplating
H01L 2224/05124
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
05001Internal layers
05099Material
051with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
05117the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
05124Aluminium [Al] as principal constituent
H01L 2224/05147
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
05001Internal layers
05099Material
051with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
05138the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
05147Copper [Cu] as principal constituent
Applicants
  • HITACHI, LTD. [JP/JP]; 6, Kanda Surugadai 4-chome Chiyoda-ku Tokyo 101-8010, JP (AllExceptUS)
  • MAITANI, Touta [JP/JP]; JP (UsOnly)
  • NISHIHARA, Shinji [JP/JP]; JP (UsOnly)
Inventors
  • MAITANI, Touta; JP
  • NISHIHARA, Shinji; JP
Agents
  • TSUTSUI, Yamato; Tsutsui & Associates N.S. Excel 301 22-45, Nishishinjuku 7-chome Shinjuku-ku Tokyo 160-0023, JP
Priority Data
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
(FR) DISPOSITIF A SEMI-CONDUCTEURS ET SON PROCEDE DE FABRICATION
Abstract
(EN)
A CSP for electrically connecting a bump electrode (2) area-arranged on a chip (1A) to a bonding pad (BP) through Cu interconnection (6), wherein the surface of the Cu interconnection (6) is covered with a barrier layer (14) to prevent Cu atoms from diffusing from the Cu interconnection (6) into a polyimide resin layer (3) because of a heating step during the manufacturing process.
(FR)
On décrit un boîtier de la taille d'une puce destiné à connecter électriquement une électrode à bosses (2), disposée dans une zone sur une puce (1A), à un plot de connexion (PC) par l'intermédiaire d'une interconnexion Cu (6); la surface de l'interconnexion Cu (6) étant recouverte d'une couche barrière (14) qui empêche les atomes Cu de se diffuser et de migrer de l'interconnexion Cu (6) dans une couche (3) de résine de polyimide du fait d'une étape de chauffage effectuée pendant le processus de fabrication.
Also published as
Latest bibliographic data on file with the International Bureau