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1. WO2000044040 - METHOD OF WIRE BONDING, SEMICONDUCTOR DEVICE, CIRCUIT BOARD, ELECTRONIC DEVICE AND WIRE BONDER

Publication Number WO/2000/044040
Publication Date 27.07.2000
International Application No. PCT/JP2000/000214
International Filing Date 19.01.2000
IPC
H01L 21/607 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
607involving the application of mechanical vibrations, e.g. ultrasonic vibrations
H01L 23/495 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488consisting of soldered or bonded constructions
495Lead-frames
CPC
H01L 2224/05553
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
0555Shape
05552in top view
05553being rectangular
H01L 2224/05599
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
05599Material
H01L 2224/05624
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
05599Material
056with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
05617the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
05624Aluminium [Al] as principal constituent
H01L 2224/32225
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
321Disposition
32151the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
32221the body and the item being stacked
32225the item being non-metallic, e.g. insulating substrate with or without metallisation
H01L 2224/4809
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
4805Shape
4809Loop shape
H01L 2224/48091
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
4805Shape
4809Loop shape
48091Arched
Applicants
  • SEIKO EPSON CORPORATION [JP/JP]; 4-1, Nishi-shinjuku 2-chome Shinjuku-ku, Tokyo 163-0811, JP (AllExceptUS)
  • KOYAMA, Yugo [JP/JP]; JP (UsOnly)
  • SAKURAI, Kazunori [JP/JP]; JP (UsOnly)
Inventors
  • KOYAMA, Yugo; JP
  • SAKURAI, Kazunori; JP
Agents
  • INOUE, Hajime ; Ogikubo TM Building, 2nd Floor 26-13, Ogikubo 5-chome Suginami-ku, Tokyo 167-0051, JP
Priority Data
11/1382522.01.1999JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) METHOD OF WIRE BONDING, SEMICONDUCTOR DEVICE, CIRCUIT BOARD, ELECTRONIC DEVICE AND WIRE BONDER
(FR) TECHNIQUE DE SOUDAGE DE FILS, DISPOSITIF SEMI-CONDUCTEUR, CARTE DE CIRCUIT IMPRIME, DISPOSITIF ELECTRONIQUE ET POSTE DE SOUDURE
Abstract
(EN)
A method of wire bonding includes arranging a plurality of leads (20) in a phantom plane (P) around a semiconductor chip (10) provided with a plurality of electrodes (12) aligned along a phantom straight line (L1); bonding wires (30) to the electrodes (12); bending the wires (30) toward leads (20) in a plane perpendicular to the phantom plane (P); and bonding the wires (30) to the leads (20).
(FR)
Cette invention concerne une technique de soudage de fils qui consiste à disposer une pluralité de fils de connexion (20) dans un plan fantôme (P) autour d'une puce semi-conductrice (10) dotée d'une pluralité d'électrodes (12) disposées le long d'une ligne droite fantôme (L1); à cintrer les fils (30) vers les fils de connexion (20) selon un plan perpendiculaire au plan fantôme (P) et à souder les fils (30) aux fils (20).
Latest bibliographic data on file with the International Bureau