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1. WO2000043902 - HIGH-SPEED PROCESSOR SYSTEM, METHOD OF USING THE SAME, AND RECORDING MEDIUM

Publication Number WO/2000/043902
Publication Date 27.07.2000
International Application No. PCT/JP2000/000278
International Filing Date 21.01.2000
Chapter 2 Demand Filed 15.08.2000
IPC
G06F 9/312 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
312Controlling loading, storing or clearing operations
G06F 9/38 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
G06F 12/08 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
G06F 15/78 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general; Data processing equipment in general
76Architectures of general purpose stored program computers
78comprising a single central processing unit
CPC
G06F 12/0811
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0806Multiuser, multiprocessor or multiprocessing cache systems
0811with multilevel cache hierarchies
G06F 15/7821
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general
76Architectures of general purpose stored program computers
78comprising a single central processing unit
7807System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
7821Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory
G06F 9/30043
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30003Arrangements for executing specific machine instructions
3004to perform operations on memory
30043LOAD or STORE instructions; Clear instruction
G06F 9/30047
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30003Arrangements for executing specific machine instructions
3004to perform operations on memory
30047Prefetch instructions; cache control instructions
G06F 9/3802
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3802Instruction prefetching
G06F 9/3879
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3877using a slave processor, e.g. coprocessor
3879for non-native instruction execution, e.g. executing a command; for Java instruction set
Applicants
  • SONY COMPUTER ENTERTAINMENT INC. [JP/JP]; 1-1, Akasaka 7-chome Minato-ku Tokyo 107-0052, JP
Inventors
  • OHBA, Akio; JP
Agents
  • YAMAMOTO, Toshitake; 301, Ogikubo Sunny Garden 28-9, Ogikubo 4-chome Suginami-ku Tokyo 167-0051, JP
Priority Data
11/1348621.01.1999JP
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) HIGH-SPEED PROCESSOR SYSTEM, METHOD OF USING THE SAME, AND RECORDING MEDIUM
(FR) PROCESSEUR A GRANDE VITESSE, METHODE D'UTILISATION ET SUPPORT D'ENREGISTREMENT
Abstract
(EN)
The invention is aimed at providing a high-speed processor system capable of performing distributed concurrent processing without requiring modification of conventional programming styles. The processor system in accordance with the invention has a CPU, a plurality of parallel DRAMs, and a plurality of cache memories arranged in a hierarchical configuration. Each of the cache memories is provided with an MPU which is binarily-compatible with the CPU and which has a function to serve as a processor.
(FR)
Cette invention a trait à un processeur à grande vitesse, capable d'exécuter un traitement parallèle réparti sans exiger une modification de styles de programmation classiques. Ce processeur se compose d'une unité centrale, de plusieurs mémoires vives dynamiques et de plusieurs antémémoires disposées selon une configuration hiérarchique. Chacune de ces antémémoires possède un microprocesseur compatible au niveau binaire avec l'unité centrale et faisant office de processeur.
Other related publications
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