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1. WO2000043895 - DRAM REFRESH MONITORING AND CYCLE ACCURATE DISTRIBUTED BUS ARBITRATION IN A MULTI-PROCESSING ENVIRONMENT

Publication Number WO/2000/043895
Publication Date 27.07.2000
International Application No. PCT/US2000/000951
International Filing Date 14.01.2000
Chapter 2 Demand Filed 15.08.2000
IPC
G06F 13/368 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
36for access to common bus or bus system
368with decentralised access control
G11C 11/406 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
406Management or control of the refreshing or charge-regeneration cycles
CPC
G06F 13/368
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
36for access to common bus or bus system
368with decentralised access control
G11C 11/406
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
406Management or control of the refreshing or charge-regeneration cycles
Applicants
  • ANALOG DEVICES, INC. [US/US]; One Technology Way P.O. Box 9106 Norwood, MA 02062-9106, US
Inventors
  • KOSLAWSKY, Robert; IL
  • GREENFIELD, Zvi; IL
  • SANDBANK, Alberto, E.; IL
Agents
  • PRITZKER, Randy, J.; Wolf, Greenfield & Sacks, P.C. 600 Atlantic Avenue Boston, MA 02210, US
Priority Data
09/235,78022.01.1999US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) DRAM REFRESH MONITORING AND CYCLE ACCURATE DISTRIBUTED BUS ARBITRATION IN A MULTI-PROCESSING ENVIRONMENT
(FR) CONTROLE DU RAFRAICHISSEMENT DE DRAM ET ARBITRAGE DE BUS DISTRIBUE CYCLIQUE PRECIS DANS UN ENVIRONNEMENT MULTITRAITEMENT
Abstract
(EN)
A multiprocessor system includes a distributed bus arbitration system in which bus arbitration takes place simultaneously on each of the multiple processors connected to the bus. Each processor has a local arbitrator of common configuration with the other local arbitrators and a dedicated request line. Each local arbitrator is connected to each dedicated request line to monitor signals on lines indicative of requests for mastership of the bus by the processors. The multiprocessor system also includes a distributed DRAM refresh system in which each processor has a local DRAM refresh controller of common configuration with the other DRAM refresh controllers. Thus, as mastership of the bus passes from one processor to the other, the new bus master's local DRAM refresh controller can continue the DRAM refresh process without requiring information to be transferred from the old bus master to the new bus master, and without duplicating DRAM refresh operations.
(FR)
Cette invention concerne un système multiprocesseur, comprenant un système d'arbitrage de bus distribué, dans lequel l'arbitrage de bus se déroule simultanément sur chacun des multiples processeurs connectés au bus. Chaque processeur possède un arbitre local de configuration commune à celle des autres arbitres locaux et une ligne de requête spécifique. Chaque arbitre local est connecté à chaque ligne de requête spécifique, afin de contrôler les signaux sur des lignes indicatives des requêtes, ce qui permet aux processeurs de superviser le bus. Le système multiprocesseur comprend également un système de rafraîchissement de DRAM distribuée, dans lequel chaque processeur possède un contrôleur de rafraîchissement de DRAM local de configuration commune à celle des autres contrôleurs de rafraîchissement de DRAM. De ce fait, comme la supervision du bus passe d'un processeur à l'autre, le contrôleur de rafraîchissement de DRAM local du nouveau bus maître peut continuer le processus de rafraîchissement de DRAM, sans que les informations aient besoin d'être transférées de l'ancien bus maître au nouveau bus maître et sans que les opérations de rafraîchissement de DRAM n'aient à être répétées.
Also published as
Latest bibliographic data on file with the International Bureau