Processing

Please wait...

Settings

Settings

1. WO2000043888 - FULL CACHE COHERENCY ACROSS MULTIPLE RAID CONTROLLERS

Publication Number WO/2000/043888
Publication Date 27.07.2000
International Application No. PCT/US2000/001921
International Filing Date 25.01.2000
Chapter 2 Demand Filed 25.08.2000
IPC
G06F 3/06 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from, or digital output to, record carriers
G06F 9/312 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
312Controlling loading, storing or clearing operations
G06F 12/08 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
CPC
G06F 11/2089
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
16Error detection or correction of the data by redundancy in hardware
20using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
2053where persistent mass storage functionality or persistent mass storage control functionality is redundant
2089Redundant storage control functionality
G06F 11/2097
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
16Error detection or correction of the data by redundancy in hardware
20using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
2097maintaining the standby controller/processing unit updated
G06F 12/0866
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0866for peripheral storage systems, e.g. disk cache
G06F 2212/262
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2212Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
26Using a specific storage system architecture
261Storage comprising a plurality of storage devices
262configured as RAID
G06F 2212/286
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2212Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
28Using a specific disk cache architecture
285Redundant cache memory
286Mirrored cache memory
Applicants
  • INTERNATIONAL BUSINESS MACHINES CORPORATION [US/US]; Armonk New York, NY 10504, US
Inventors
  • HUBIS, Walter, A.; US
Agents
  • ANANIAN, R., Michael ; Flehr Hohbach Test Albritton & Herbert LLP Suite 3400 4 Embarcadero Center San Francisco, CA 94111-4187, US
Priority Data
09/236,50425.01.1999US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) FULL CACHE COHERENCY ACROSS MULTIPLE RAID CONTROLLERS
(FR) COHERENCE DE MEMOIRE CACHE COMPLETE SUR PLUSIEURS ORGANES DE COMMANDE DE RESEAU REDONDANT DE DISQUES INDEPENDANTS (RAID)
Abstract
(EN)
A method for providing cache coherency in a RAID system (100) in which multiple RAID controllers (104) provide read/write access to shared storage devices (108) for multiple host computers (102). Each controller includes read (114), write (116) and write mirror (118) caches and the controllers and the shared storage devices are coupled to one another via common backend buses (110). Whenever a controller receives a write command (302) from a host the controller writes the data to the shared devices, its write cache and the write mirror caches of the other controllers. Whenever a controller receives a read command (320) from a host the controller attempts to return the requested data from its write mirror cache, write cache and read cache and the storage devices, in that order.
(FR)
L'invention concerne un procédé permettant d'assurer la cohérence de mémoire cache dans un système RAID (100) au sein duquel plusieurs organes de commande RAID (104) offrent un accès lecture/écriture à des dispositifs de stockage partagés (108), pour une pluralité d'ordinateurs hôtes (102). Chaque organe de commande comporte des caches de lecture (114), d'écriture (116) et d'écriture miroir (118), et les organes de commande ainsi que les dispositifs de stockage partagés sont couplés mutuellement via des bus de système principal communs (110). Chaque fois qu'il reçoit une commande d'écriture (302) depuis un hôte, l'organe de commande transmet les données en écriture aux dispositifs de stockage partagés, à son cache d'écriture et aux caches d'écriture miroir des autres organes de commande. Chaque fois qu'il reçoit une commande de lecture (320) depuis un hôte, l'organe de commande tente de renvoyer les données demandées depuis son cache d'écriture miroir, ses caches d'écriture et de lecture et les dispositifs de stockage, dans cet ordre.
Latest bibliographic data on file with the International Bureau