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1. WO2000042659 - SYSTEM AND METHOD FOR ESD PROTECTION

Publication Number WO/2000/042659
Publication Date 20.07.2000
International Application No. PCT/US2000/000999
International Filing Date 15.01.2000
Chapter 2 Demand Filed 14.08.2000
IPC
H01F 17/00 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
17Fixed inductances of the signal type
H01L 23/522 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 27/02 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/08 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
08including only semiconductor components of a single kind
H03B 5/12 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
BGENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
5Generation of oscillations using amplifier with regenerative feedback from output to input
08with frequency-determining element comprising lumped inductance and capacitance
12active element in amplifier being semiconductor device
H03B 5/36 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
BGENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
5Generation of oscillations using amplifier with regenerative feedback from output to input
30with frequency-determining element being electromechanical resonator
32being a piezo-electric resonator
36active element in amplifier being semiconductor device
CPC
H01F 17/0006
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
17Fixed inductances of the signal type
0006Printed inductances
H01F 17/0013
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
17Fixed inductances of the signal type
0006Printed inductances
0013with stacked layers
H01F 2017/0053
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
17Fixed inductances of the signal type
0006Printed inductances
0053with means to reduce eddy currents
H01F 2021/125
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
21Variable inductances or transformers of the signal type
12discontinuously variable, e.g. tapped
125Printed variable inductor with taps, e.g. for VCO
H01L 2224/05554
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
0555Shape
05552in top view
05554being square
H01L 23/5227
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another ; , i.e. interconnections, e.g. wires, lead frames
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
5227Inductive arrangements or effects of, or between, wiring layers
Applicants
  • BROADCOM CORPORATION [US/US]; 16215 Alton Parkway Irvine, CA 92618-3616, US (AllExceptUS)
  • WOO, Agnes, N. [US/US]; US (UsOnly)
  • KINDSFATER, Kenneth, R. [US/US]; US (UsOnly)
  • LU, Fang [--/US]; US (UsOnly)
  • VORENKAMP, Pieter [NL/US]; US (UsOnly)
Inventors
  • WOO, Agnes, N.; US
  • KINDSFATER, Kenneth, R.; US
  • LU, Fang; US
  • VORENKAMP, Pieter; US
Agents
  • RAHN, LeRoy, T.; Christie, Parker & Hale LLP P.O. Box 7068 Pasadena, CA 91109-7068, US
Priority Data
09/439,10112.11.1999US
60/116,00315.01.1999US
60/117,32226.01.1999US
60/122,75425.02.1999US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) SYSTEM AND METHOD FOR ESD PROTECTION
(FR) SYSTEME ET PROCEDE DE PROTECTION CONTRE LES DECHARGES ELECTROSTATIQUES
Abstract
(EN)
An integrated circuit ESD protection system comprises: a local power supply bus, a local ground bus, a first local ESD clamp, and ESD ground bus disposed between local power supply and ground busses and coupled to the local power supply bus through the first local ESD clamp, and coupled to the local ground bus through the second ESD clamp. The local power supply bus, the local ground bus, the first ESD clamp, the second ESD clamp and the ESD ground bus are disposed on a substrate. A reduced capacitance bonding pad is disposed on the substrate. A shunting ggNMOS ESD structure triggered by a divider circuit comprises a gate boosting structure disposed in an n-well that is coupled to the bonding pad.
(FR)
L'invention porte sur sur un récepteur intégré à sélection de canaux et réjection d'image mis en oeuvre sensiblement dans un circuit intégré CMOS simple. Un préamplificateur d'ondes fournit une atténuation programmable et utilise un amplificateur à faible bruit et gain programmable. Un circuit de conversion de fréquences utilise avantageusement des filtres LC intégrés au substrat associés à des mélangeurs à réjection simple pouvant produire une réjection de fréquence d'image suffisante. La syntonisation des filtres et la compensation de température du facteur Q des inductances sont effectuées sur la puce. Les filtres mettent en oeuvre des inductances spirales à plusieurs pistes. Les filtres sont syntonisés au moyen d'oscillateurs locaux servant à syntoniser un filtre de remplacement et par échelonnement des fréquences, lesquelles fournissent les valeurs des composants des filtres relativement à celles du filtre en cours de syntonisation. La planification des fréquences associée au filtrage assure une réjection d'image additionnelle. L'intérêt des procédés de génération de signaux par oscillateurs locaux sur la puce découle du choix de l'oscillation locale en boucle à phase asservie (PLL) hors bande et de la synthèse directe pour l'oscillateur local intra-bande. Les oscillateurs à tension variable utilisés dans les boucles à phase asservie sont centrés au moyen d'un circuit de commande conçu pour centrer la plage de la capacité de syntonisation. Un oscillateur à quartz différentiel peut avantageusement servir de fréquence de référence. La transmission de signaux différentiels est avantageusement mise en oeuvre dans l'ensemble du récepteur. La protection contre les décharges électrostatiques (ESD) est assurée par un anneau support et une structure de fixation ESD qui préserve l'intégrité des signaux. L'invention concerne en outre des shunts disposés sur chaque broche pour désamorcer l'accumulation de la charge électrostatique. Les shunts mettent en oeuvre une structure d'amplification de porte pour assurer une performance RF suffisante des petits signaux et une charge parasite minimale.
Also published as
Latest bibliographic data on file with the International Bureau