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1. WO2000042654 - ELECTRONIC SEMICONDUCTOR MODULE

Publication Number WO/2000/042654
Publication Date 20.07.2000
International Application No. PCT/DE1999/004085
International Filing Date 23.12.1999
IPC
H01L 23/36 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
34Arrangements for cooling, heating, ventilating or temperature compensation
36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
H01L 23/64 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
58Structural electrical arrangements for semiconductor devices not otherwise provided for
64Impedance arrangements
CPC
H01L 2224/05599
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
05599Material
H01L 2224/48091
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
4805Shape
4809Loop shape
48091Arched
H01L 2224/48227
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
481Disposition
48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
48221the body and the item being stacked
48225the item being non-metallic, e.g. insulating substrate with or without metallisation
48227connecting the wire to a bond pad of the item
H01L 2224/48228
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
481Disposition
48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
48221the body and the item being stacked
48225the item being non-metallic, e.g. insulating substrate with or without metallisation
48227connecting the wire to a bond pad of the item
48228the bond pad being disposed in a recess of the surface of the item
H01L 2224/484
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
484Connecting portions
H01L 2224/85399
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
85using a wire connector
8538Bonding interfaces outside the semiconductor or solid-state body
85399Material
Applicants
  • ROBERT BOSCH GMBH [DE/DE]; Postfach 30 02 20 D-70442 Stuttgart, DE (AllExceptUS)
  • KOELLE, Gerhard [DE/DE]; DE (UsOnly)
  • JACOB, Wolfgang [DE/DE]; DE (UsOnly)
  • TSCHENTSCHER, Harald [DE/DE]; DE (UsOnly)
  • REES, Stephan [DE/DE]; DE (UsOnly)
Inventors
  • KOELLE, Gerhard; DE
  • JACOB, Wolfgang; DE
  • TSCHENTSCHER, Harald; DE
  • REES, Stephan; DE
Priority Data
199 00 603.211.01.1999DE
Publication Language German (DE)
Filing Language German (DE)
Designated States
Title
(DE) ELEKTRONISCHES HALBLEITERMODUL
(EN) ELECTRONIC SEMICONDUCTOR MODULE
(FR) MODULE SEMI-CONDUCTEUR ELECTRONIQUE
Abstract
(DE)
Zur Verbesserung der Wärmeableitung und zur Reduzierung von parasitären Induktivitäten in einem elektronischen Halbleitermodul, welches ein Trägersubstrat (1) mit einer elektrisch isolierenden Schicht (2), einer auf der Oberseite der isolierenden Schicht angeordneten Metallschicht (4), in der durch Strukturieren Leiterbahnen (4a) ausgebildet sind, und einen auf die Unterseite der isolierenden Schicht aufgebrachten metallischen Kühlkörper (3) sowie wenigstens ein auf dem Trägersubstrat angeordnetes Halbleiterbauelement (20) aufweist, wird vorgeschlagen, die elektrisch isolierende Schicht mit wenigstens einer Aussparung (13) zu versehen und wenigstens eine auf der von dem Trägersubstrat abgewandten Oberseite des Halbleiterbauelementes vorgesehene Anschlußfläche (22) mit einem Kontaktelement (12) elektrisch zu verbinden, welches durch die Aussparung hindurch direkt auf den metallischen Kühlkörper kontaktiert ist.
(EN)
In order to improve the dissipation of heat and to reduce parasitic inductivities in an electronic semiconductor module that consists of a carrier substrate (1) with an electrically insulating layer (2), a metal layer (4) arranged on the top surface of the insulating layer whereby strip conductors (4a) are configured inside said metal layer, and a metal cooling body (3) that is placed on the bottom side of the insulating layer, in addition to at least one semiconductor element arranged on the carrier substrate, the electrically insulating layer that is provided with at least one recess (13) and at least one connecting surface (22) that is located on the top side of the semiconductor element opposite the carrier substrate is electrically connected to a contact element (2) that is directly brought into contact with the metal cooling body via the recess.
(FR)
L'invention concerne un module semi-conducteur électronique comprenant un substrat servant de support (1) présentant une couche électriquement isolante (2), une couche métallique (4) appliquée sur le recto de la couche isolante, dans laquelle sont formées, par structuration, des pistes de conducteurs (4a), et un corps de refroidissement métallique (3) appliqué sur le verso de la couche isolante, ainsi qu'au moins un composant semi-conducteur (20) disposé sur le substrat-support, et a pour but d'améliorer la dissipation de chaleur et de réduire les inductivités parasites dans un tel module. A cet effet, l'invention est caractérisée en ce que la couche électriquement isolante comporte au moins un évidement (13), et en ce qu'au moins une surface de raccordement (22) prévue sur le recto du composant semi-conducteur, opposé au substrat-support est connectée électriquement à un élément de contact (12) qui, par ledit évidement, est maintenu en contact directement sur le corps de refroidissement métallique.
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