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1. WO2000042500 - NOT REPORTED JUMP BUFFER

Publication Number WO/2000/042500
Publication Date 20.07.2000
International Application No. PCT/SE1999/002361
International Filing Date 15.12.1999
Chapter 2 Demand Filed 19.07.2000
IPC
G06F 9/38 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
CPC
G06F 9/3836
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3836Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
G06F 9/3838
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3836Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
3838Dependency mechanisms, e.g. register scoreboarding
G06F 9/3842
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3836Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
3842Speculative instruction execution
G06F 9/3855
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3836Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
3855Reordering, e.g. using a queue, age tags
G06F 9/3857
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3836Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
3857Result writeback, i.e. updating the architectural state
Applicants
  • TELEFONAKTIEBOLAGET LM ERICSSON [SE/SE]; S-126 25 Stockholm, SE
Inventors
  • BERGLIN, Pär, David; SE
  • PETTERSSON, Hans, Christian; SE
Agents
  • STENBORG, Anders ; Aros Patent AB Box 1544 S-751 45 Uppsala, SE
Priority Data
9900042-411.01.1999SE
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) NOT REPORTED JUMP BUFFER
(FR) MEMOIRE TAMPON POUR SAUTS NON SIGNALES
Abstract
(EN)
The present invention achieves a fast handling of the predicted jumps by introducing an additional buffer (20) for not reported predicted jump instructions in a reorder buffer. This additional buffer (20) is separate from the main buffer (10) and is supplied only with information associated with instructions related to predicted jumps. A predicted jump instruction is preferably stored both in the main buffer (10) and the additional buffer (20). The additional buffer operates in parallel with the main buffer (10) and is designed as a linear first-in-first-out queue. The first not reported jump is then always easily available at the top of the queue for evaluating the jump conditions. If a mispredicted jump is determined, the reorder buffer is flushed by a flush generator unit (42).
(FR)
L'invention concerne permet un traitement rapide des sauts prédits, grâce à l'introduction dans une mémoire tampon de réordonnancement d'une mémoire (20) tampon additionnelle pour les instructions de sauts prédits non signalés. Cette mémoire (20) tampon additionnelle est séparée de la mémoire (10) principale et reçoit uniquement les informations associées aux instructions concernant des sauts prédits. Une instruction concernant un saut prédit est mémorisée de préférence à la fois dans la mémoire (10) tampon principale et dans la mémoire (20) tampon additionnelle. La mémoire tampon additionnelle fonctionne en parallèle avec la mémoire (10) tampon principale et présente une configuration de file d'attente linéaire. Il est toujours facile d'accéder au premier saut non signalé au début de la file lors d'une évaluation des conditions de saut. Si une erreur de prédiction concernant un saut est détectée, la mémoire tampon de réordonnancement est vidée par une unité (42) de vidange.
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