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1. WO2000042499 - METHODS AND APPARATUS TO DYNAMICALLY RECONFIGURE THE INSTRUCTION PIPELINE OF INDIRECT VERY LONG INSTRUCTION WORD SCALABLE PROCESSOR

Publication Number WO/2000/042499
Publication Date 20.07.2000
International Application No. PCT/US2000/000569
International Filing Date 10.01.2000
Chapter 2 Demand Filed 13.06.2000
IPC
G06F 9/30 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
G06F 9/318 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
318with operation extension or modification
G06F 9/38 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
CPC
G06F 9/30058
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30003Arrangements for executing specific machine instructions
3005to perform operations for flow control
30058Conditional branch instructions
G06F 9/30076
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30003Arrangements for executing specific machine instructions
30076to perform miscellaneous control operations, e.g. NOP
G06F 9/30079
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30003Arrangements for executing specific machine instructions
30076to perform miscellaneous control operations, e.g. NOP
30079Pipeline control instructions
G06F 9/30181
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30181Instruction operation extension or modification
G06F 9/30189
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30181Instruction operation extension or modification
30189according to execution mode, e.g. mode flag
G06F 9/3802
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3802Instruction prefetching
Applicants
  • BOPS INCORPORATED [US/US]; Suite 210 6340 Quadrangle Drive Chapel Hill, NC 27514, US
Inventors
  • REVILLA, Juan, Guillermo; US
  • BARRY, Edwin, Frank; US
  • MARCHAND, Patrick, Rene; US
  • PECHANEK, Gerald, G.; US
Agents
  • PRIEST, Peter, H.; Law Offices of Peter H. Priest 529 Dogwood Drive Chapel Hill, NC 27516, US
Priority Data
09/228,37412.01.1999US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) METHODS AND APPARATUS TO DYNAMICALLY RECONFIGURE THE INSTRUCTION PIPELINE OF INDIRECT VERY LONG INSTRUCTION WORD SCALABLE PROCESSOR
(FR) PROCEDES ET DISPOSITIFS DE RECONFIGURATION DYNAMIQUE D'UN PIPELINE D'INSTRUCTION D'UN PROCESSEUR POUVANT ETRE ECHELONNE PAR DES MOTS D'INSTRUCTION TRES LONGS
Abstract
(EN)
A ManArray processor pipeline design addresses an indirect VLIW memory (206) access problem without increasing branch latency by providing a dynamically reconfigurable instruction pipeline for SIWs (241, 243, ..., 249) requiring a VLIW to be fetched. By introducing an additional cycle in the pipeline only when a VLIW fetch is required, the present invention solves the VLIW memory (206) access problem. The pipeline stays in an expanded state, in general, until a branch type or load VLIW memory (206) type operation is detected returning the pipeline to a compressed pipeline operation. By compressing the pipeline when a branch type operation is detected, the need for an additional cycle for the branch operation is avoided. Consequently, the shorter compressed pipeline provides more efficient performance for branch intensive control code as compared to a fixed pipeline with an expanded number of pipeline stages. In addition, the dynamic reconfigurable pipeline is scalable allowing each processing element (PE) in an array of PEs to expand and compress the pipeline in synchronism allowing the iVLIW operations to execute independently in each PE. This is accomplished by having distributed pipelines in operation in parallel, one in each PE and in the controller sequence processor (SP).
(FR)
Selon l'invention, une architecture de pipeline de processeur du type à réseaux multiples «ManArray» permet l'accès à une mémoire indirecte (206) de mots d'instruction très longs, sans augmenter le temps de latence de ramification, étant donné que ce pipeline d'instruction peut être reconfiguré de manière dynamique pour des mots d'instruction courts (241, 243, ... 249) nécessitant l'extraction d'un mot très long. En introduisant un cycle supplémentaire dans le pipeline, seulement lorsque l'extraction d'un mot très long est requise, l'invention résout le problème d'accès à la mémoire de mots d'instruction très longs (206). Le pipeline reste à l'état élargi, en général, jusqu'à ce qu'une opération de mémoire de mots d'instruction très longs (206) soit détectée, renvoyant le pipeline à une opération de pipeline compressé. En compressant le pipeline, lorsqu'une opération du type ramification est détectée, il n'est pas nécessaire d'avoir un cycle complémentaire pour une opération de ramification. En conséquence, le pipeline plus court, compressé, est doté de performances plus efficaces pour un code de commande intensif de ramification, par comparaison avec le pipeline fixe possédant un certain nombre élargi d'étages de pipeline. En outre, ce pipeline que l'on peut reconfigurer de manière dynamique peut être échelonné, de sorte qu'il permet à chaque élément de traitement d'un groupe d'éléments de traitement d'élargir et compresser le pipeline de manière synchronisée, permettant que les opérations de mots d'instruction très longs puissent s'exécuter indépendamment dans chaque élément de traitement, ce qui peut se faire par le biais de pipelines répartis et fonctionnant en parallèle, un dans chaque élément de traitement et dans le processeur de séquences du module de commande.
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