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1. WO2000042483 - LOW THRESHOLD MOS TWO PHASE NEGATIVE CHARGE PUMP

Publication Number WO/2000/042483
Publication Date 20.07.2000
International Application No. PCT/US1999/000763
International Filing Date 14.01.1999
Chapter 2 Demand Filed 14.08.2000
IPC
H01L 27/02 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H02M 3/07 2006.01
HELECTRICITY
02GENERATION, CONVERSION, OR DISTRIBUTION OF ELECTRIC POWER
MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
3Conversion of dc power input into dc power output
02without intermediate conversion into ac
04by static converters
06using resistors or capacitors, e.g. potential divider
07using capacitors charged and discharged alternately by semiconductor devices with control electrode
CPC
H01L 27/0222
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
0203Particular design considerations for integrated circuits
0214for internal polarisation, e.g. I2L
0218of field effect structures
0222Charge pumping, substrate bias generation structures
H02M 2003/078
HELECTRICITY
02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
3Conversion of dc power input into dc power output
02without intermediate conversion into ac
04by static converters
06using resistors or capacitors, e.g. potential divider
07using capacitors charged and discharged alternately by semiconductor devices with control electrode ; , e.g. charge pumps
073Charge pumps of the SCHENKEL type
078with means for reducing the back bias effect, i.e. the effect which causes the threshold voltage of transistors to increase as more stages are added to the converter
H02M 3/073
HELECTRICITY
02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
3Conversion of dc power input into dc power output
02without intermediate conversion into ac
04by static converters
06using resistors or capacitors, e.g. potential divider
07using capacitors charged and discharged alternately by semiconductor devices with control electrode ; , e.g. charge pumps
073Charge pumps of the SCHENKEL type
Applicants
  • MACRONIX INTERNAITONAL CO., LTD. [--/--]; No. 3, Creation Road, 3rd Science-Based Industrial Park Hsinchu, TW (AllExceptUS)
  • SHIAU, Tzing-Huei [--/--]; TW (UsOnly)
  • LIN, Yu-Shen [--/--]; TW (UsOnly)
  • WAN, Ray-Lin [US/US]; US (UsOnly)
Inventors
  • SHIAU, Tzing-Huei; TW
  • LIN, Yu-Shen; TW
  • WAN, Ray-Lin; US
Agents
  • HAYNES, Mark; Haynes & Beffel P.O. Box 366 Half Moon Bay, CA 94019, US
Priority Data
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) LOW THRESHOLD MOS TWO PHASE NEGATIVE CHARGE PUMP
(FR) POMPE DE CHARGE NEGATIVE A DEUX PHASES COMPRENANT UN MOS A SEUIL REDUIT
Abstract
(EN)
A triple well charge pump comprises a first transistor connected in a diode configuration having a first channel terminal (61), nominally the source, coupled to a first node, and the second channel terminal (62), nominally the drain, coupled to its gate (64) and to a second node (66). A first capacitor (65) has a first terminal coupled to the first node of the charge pump, and a second terminal adapted to receive a first clock signal (CK). A second transistor has a first channel terminal (72) coupled to the second node of the charge pump, and a second channel terminal (73) coupled to its gate (74) and to a third node. A second capacitor (85) has a first terminal coupled to the second node, and second terminal adapted to receive a second clock signal (CKB). The first and second transistors comprise a first region and a second region having a first conductivity type (n+) providing the first and second channel terminals respectively, a channel region (57) in which the first and second regions are formed having a second conductivity type, and an isolation well (51) having the first conductivity type in a semiconductor substrate (50). The first and second regions, the channel region and the isolation well form a parasitic bipolar junction transistor that has a threshold voltage. The channel region has a doping concentration establishing a threshold voltage for the MOS transistor which is less than the threshold voltage of the parasitic bipolar junction transistor. The clock signals have sloped rising and falling edges.
(FR)
Cette invention concerne une pompe de charge à puits triple comprenant un premier transistor qui est connecté en configuration de diode et qui comprend une première borne de canal (61), ou source, couplée à un premier noeud, ainsi qu'une seconde borne de canal (62), ou drain, couplée à sa grille (64) et à un deuxième noeud (66). Un premier condensateur (65) possède une première borne qui est couplée au premier noeud de la pompe de charge, ainsi qu'une seconde borne qui va recevoir un premier signal d'horloge (CK). Un second transistor comprend une première borne de canal (72) couplée au deuxième noeud de la pompe de charge, ainsi qu'une seconde borne de canal (73) couplée à sa grille (74) et à un troisième noeud. Un second condensateur (85) possède une première borne qui est couplée au deuxième noeud, ainsi qu'une seconde borne qui va recevoir un second signal d'horloge (CKB). Le premier et le second transistors comprennent une première et une seconde zones possédant un premier type de conductivité (n+) alimentant la première et la seconde bornes de canal respectivement, une zone canal (57) dans laquelle la première et la seconde zones possèdent un second type de conductivité, et un puits d'isolation (51) possédant le premier type de conductivité et se situant dans un substrat semiconducteur (50). La première et la seconde zones, la zone canal et le puits d'isolation forment un transistor à jonction bipolaire parasite qui possède une tension seuil. La zone canal possède une concentration de dopage qui définit la tension seuil du transistor MOS de sorte qu'elle soit inférieure à la tension seuil du transistor à jonction bipolaire parasite. Les signaux d'horloge possèdent une courbe ascendante en pente et des flancs descendants.
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