Processing

Please wait...

Settings

Settings

1. WO2000041447 - METHOD FOR PRODUCING A MULTILAYER PRINTED CIRCUIT BOARD

Publication Number WO/2000/041447
Publication Date 13.07.2000
International Application No. PCT/CH1999/000625
International Filing Date 24.12.1999
Chapter 2 Demand Filed 24.06.2000
IPC
H05K 1/11 2006.01
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1Printed circuits
02Details
11Printed elements for providing electric connections to or between printed circuits
H05K 3/00 2006.01
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3Apparatus or processes for manufacturing printed circuits
H05K 3/46 2006.01
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3Apparatus or processes for manufacturing printed circuits
46Manufacturing multi-layer circuits
CPC
H05K 1/115
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1Printed circuits
02Details
11Printed elements for providing electric connections to or between printed circuits
115Via connections; Lands around holes or via connections
H05K 2201/09509
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
2201Indexing scheme relating to printed circuits covered by H05K1/00
09Shape and layout
09209Shape and layout details of conductors
095Conductive through-holes or vias
09509Blind vias, i.e. vias having one side closed
H05K 2201/0959
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
2201Indexing scheme relating to printed circuits covered by H05K1/00
09Shape and layout
09209Shape and layout details of conductors
095Conductive through-holes or vias
0959Plated through-holes or plated blind vias filled with insulating material
H05K 2201/096
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
2201Indexing scheme relating to printed circuits covered by H05K1/00
09Shape and layout
09209Shape and layout details of conductors
095Conductive through-holes or vias
096Vertically aligned vias, holes or stacked vias
H05K 2203/0207
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
2203Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
02Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
0207Partly drilling through substrate until a controlled depth, e.g. with end-point detection
H05K 2203/0353
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
2203Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
03Metal processing
0353Making conductive layer thin, e.g. by etching
Applicants
  • PPC ELECTRONIC AG [CH/CH]; Riedstrasse 2 CH-6330 Cham, CH (AllExceptUS)
  • WIDMER, Thomas [CH/CH]; CH (UsOnly)
Inventors
  • WIDMER, Thomas; CH
Agents
  • OTTOW, Jens, M.; Hug Interlizenz AG Nordstrasse 31 CH-8035 Zürich, CH
Priority Data
7/9905.01.1999CH
Publication Language German (DE)
Filing Language German (DE)
Designated States
Title
(DE) VERFAHREN ZUM HERSTELLEN EINER MEHRLAGIGEN LEITERPLATTE
(EN) METHOD FOR PRODUCING A MULTILAYER PRINTED CIRCUIT BOARD
(FR) PROCEDE DE FABRICATION D'UNE CARTE DE CIRCUITS IMPRIMES MULTICOUCHE
Abstract
(DE)
Bei einem Verfahren zum Herstellen einer mehrlagigen Leiterplatte, die durch das Verpressen von jeweils aus einer Leiterschicht (24, 25, 31, 32) und einer Isolierschicht (16, 17; 28, 29) bestehenden Laminatlagen (20, 30, 40, 50) mit einem Laminatkern (10) aufgebaut wird, werden die Durchkontaktieröffnungen (33, 34) zwischen den Leiterschichten (24, 32 bzw. 25, 31) mittels Laserstrahlbohren durch die einzelnen Laminatlagen (40, 50) erzeugt und anschliessend durchmetallisiert.
(EN)
The invention relates to a method for producing a multilayer printed circuit board which is produced by bonding laminate layers (20, 30, 40, 50) which each consist of a conductor layer (24, 25, 31, 32) and an insulating layer (16, 17; 28, 29) to a laminate core (10). According to the invention the via holes (33, 34) between the conductor layers (24, 32 and 25, 31) are formed by laser drilling through the individual laminate layers (40, 50) and then plated through.
(FR)
Cette invention concerne un procédé de fabrication d'une carte de circuits imprimés multicouche. Selon ce procédé de fabrication, des couches de matériau stratifié (20, 30, 40 50), formé d'une couche de matériau conducteur (24, 25, 31, 32) et d'une couche de matériau isolant (16, 17; 28, 29), sont pressées autour d'un coeur (10). A l'aide d'un faisceau laser, on réalise des trous (33, 34) entre les couches conductrices (25, 31 ou 24, 32), à travers les couches de matériau stratifié (40, 50). Ces trous sont ensuite métallisés.
Also published as
Latest bibliographic data on file with the International Bureau