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1. WO2000041446 - CIRCUIT BOARD FEATURES WITH REDUCED PARASITIC CAPACITANCE AND METHOD THEREFOR

Publication Number WO/2000/041446
Publication Date 13.07.2000
International Application No. PCT/US1999/028534
International Filing Date 02.12.1999
IPC
H01F 17/00 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
17Fixed inductances of the signal type
H01F 41/04 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
41Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
02for manufacturing cores, coils or magnets
04for manufacturing coils
H05K 1/16 2006.01
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1Printed circuits
16incorporating printed electric components, e.g. printed resistor, capacitor, inductor
H05K 3/00 2006.01
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3Apparatus or processes for manufacturing printed circuits
H05K 3/46 2006.01
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3Apparatus or processes for manufacturing printed circuits
46Manufacturing multi-layer circuits
CPC
H01F 17/0013
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
17Fixed inductances of the signal type
0006Printed inductances
0013with stacked layers
H01F 41/041
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
41Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
02for manufacturing cores, coils, or magnets
04for manufacturing coils
041Printed circuit coils
H01F 41/046
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
41Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
02for manufacturing cores, coils, or magnets
04for manufacturing coils
041Printed circuit coils
046structurally combined with ferromagnetic material
H05K 1/165
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1Printed circuits
16incorporating printed electric components, e.g. printed resistor, capacitor, inductor
165incorporating printed inductors
H05K 2201/0187
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
2201Indexing scheme relating to printed circuits covered by H05K1/00
01Dielectrics
0183Dielectric layers
0187with regions of different dielectrics in the same layer, e.g. in a printed capacitor for locally changing the dielectric properties
H05K 2201/0355
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
2201Indexing scheme relating to printed circuits covered by H05K1/00
03Conductive materials
0332Structure of the conductor
0335Layered conductors or foils
0355Metal foils
Applicants
  • MOTOROLA INC. [US/US]; 1303 East Algonquin Road Schaumburg, IL 60196, US
Inventors
  • DUNN, Gregory, J.; US
  • LACH, Larry; US
  • SAVIC, Jovica; US
  • BEUHLER, Allyson; US
  • SIMONS, Everett; US
Agents
  • FEKETE, Douglas, D. ; Motorola Inc. Intellectual Property Dept. 1303 East Algonquin Road Schaumburg, IL 60196, US
Priority Data
09/224,01131.12.1998US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) CIRCUIT BOARD FEATURES WITH REDUCED PARASITIC CAPACITANCE AND METHOD THEREFOR
(FR) CARTE DE CIRCUIT IMPRIME AVEC CAPACITE PARASITE REDUITE ET SON PROCEDE DE FABRICATION
Abstract
(EN)
A method for fabricating circuit board conductors (24A & 24B) generally entails forming a metal layer (24) on a positive-acting photodielectric layer (22), and etching the metal layer to form at least two conductor traces (24A & 24B) that cover separate regions of the photodielectric layer while exposing a third region therebetween. The third region of the photodielectric layer is developed using the two traces as a photomask and removed. Thus, the traces are not only separated by a void (30) formed when the metal layer was etched, but are also separated by the opening (32) formed in the photodielectric layer by the removal of the third region of the photodielectric layer. A ferrite-filled polymer may also be deposited in the void and opening to form a ferrite core (34). Traces formed in accordance with the above may be formed as adjacent and parallel conductors or adjacent inductor windings of an integral inductor.
(FR)
Cette invention concerne un procédé de fabrication de conducteurs sur cartes de circuit imprimé (24A et 24B) consistant de façon générale à former une couche métallique (24) sur une couche photo-diélectrique à action positive (22), et à graver cette couche métallique pour obtenir au moins deux traces conductrices (24A et 24B) qui recouvrent des régions distinctes de la couche photo-diélectrique tout en exposant une troisième région intermédiaire. Cette troisième région de la couche photo-diélectrique est développée au moyen de deux traces faisant office de masque photographique, puis retirée. Ainsi, les traces sont séparées non seulement par le vide (30) formé au moment de la gravure de la couche métallique, mais aussi par l'ouverture (132) créée dans la couche photo-diélectrique par le retrait de la troisième région de ladite couche. Les traces obtenues selon le procédé ci-dessus peuvent constituées des conducteurs adjacents ou parallèles ou des enroulements inducteurs adjacents dans un inducteur intégré.
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