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1. WO2000041243 - FIELD ISOLATED INTEGRATED INJECTION LOGIC GATE

Publication Number WO/2000/041243
Publication Date 13.07.2000
International Application No. PCT/EP1999/010213
International Filing Date 17.12.1999
IPC
H01L 21/8226 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8222Bipolar technology
8226comprising merged transistor logic or integrated injection logic
H01L 27/02 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
CPC
H01L 21/8226
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8222Bipolar technology
8226comprising merged transistor logic or integrated injection logic
H01L 27/0237
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
0203Particular design considerations for integrated circuits
0214for internal polarisation, e.g. I2L
0229of bipolar structures
0233Integrated injection logic structures [I2L]
0237using vertical injector structures
Applicants
  • KONINKLIJKE PHILIPS ELECTRONICS N.V. [NL/NL]; Groenewoudseweg 1 NL-5621 BA Eindhoven, NL
Inventors
  • CHEN, Chun-Yu; NL
  • FERRU, Gilles, M.; NL
  • BARDY, Serge; NL
Agents
  • HOUBIERS, Ernest, E., M., G.; Internationaal Octrooibureau B.V. Prof. Holstlaan 6 NL-5656 AA Eindhoven, NL
Priority Data
09/222,90530.12.1998US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) FIELD ISOLATED INTEGRATED INJECTION LOGIC GATE
(FR) PORTE LOGIQUE INTEGREE A INJECTION ISOLEE PAR CHAMP
Abstract
(EN)
An integrated injection logic device is provided in which each collector of an I2L gate is isolated by a field oxide ('FOX'), or by other suitable isolation such as, for example, an isolation trench. The connection of the base to the collectors, between the base contact region and the bottom of the collectors, is made underneath the field oxide using a buried p type layer (TN3 in the Figures illustrating the invention). Because both silicide and heavy implant p+ implant is present at the base contact point only, the recombination current is reduced. This reduces the current loss when compared to the current loss of the known device. Additionally, current gain is also improved by placing a deep base implant close to the emitter of the upside down NPN transistor in the integrated logic device. The area of the base and the area of the collectors is decoupled, i.e. one can adjust the base to collector areas and the base contact area, independently to control the total base current, thus allowing more freedom in layout optimization of the I2L gate and allowing more freedom in optimizing the gain of the I2L gate.
(FR)
L'invention concerne un dispositif logique intégré à injection dans lequel chaque collecteur d'une porte I2L est isolé par un oxyde de champ ('FOX'), ou par une autre isolation appropriée telle que, par exemple, une tranchée d'isolation. La connexion de la base aux collecteurs, entre la région de contact de base et le fond des collecteurs est effectuée au-dessous de l'oxyde de champ à l'aide d'une couche de type p enfouie (TL3 dans les figures illustrant l'invention). Etant donné qu'à la fois du siliciure et un implant P+ à implants lourds sont présents uniquement au niveau de point de contact, le courant de recombinaison est réduit. Ceci réduit la perte de courant comparée à la perte de courant du dispositif connu. De plus, le gain du courant est également amélioré par mise en place d'un implant de base profond à proximité de l'émetteur du transistor NPN renversé dans le dispositif logique intégré. La surface de la base et la surface des collecteurs est découplée, c'est-à-dire que l'on peut ajuster les surfaces entre la base et les collecteurs et la surface de contact de base, indépendamment, afin de réguler le courant total de la base, permettant ainsi une plus grande liberté d'optimisation du tracé de la porte I2L et permettant davantage de liberté pour optimiser le gain de la porte I2L.
Also published as
Latest bibliographic data on file with the International Bureau