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1. WO2000041238 - ELECTRICALLY PROGRAMMABLE MEMORY CELL ARRANGEMENT AND METHOD FOR THE PRODUCTION THEREOF

Publication Number WO/2000/041238
Publication Date 13.07.2000
International Application No. PCT/DE2000/000006
International Filing Date 03.01.2000
Chapter 2 Demand Filed 08.08.2000
IPC
H01L 21/8247 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology
8239Memory structures
8246Read-only memory structures (ROM)
8247electrically-programmable (EPROM)
H01L 27/115 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
CPC
H01L 27/115
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
H01L 27/11517
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11517with floating gate
Applicants
  • INFINEON TECHNOLOGIES AG [DE/DE]; St.-Martin-Str. 53 D-81541 München, DE (AllExceptUS)
  • HOFMANN, Franz [DE/DE]; DE (UsOnly)
  • WILLER, Josef [DE/DE]; DE (UsOnly)
Inventors
  • HOFMANN, Franz; DE
  • WILLER, Josef; DE
Agents
  • EPPING HERMANN & FISHER GBR; St.-Martin-Str. 53 D-81541 München, DE
Priority Data
199 00 507.908.01.1999DE
Publication Language German (DE)
Filing Language German (DE)
Designated States
Title
(DE) ELEKTRISCH PROGRAMMIERBARE SPEICHERZELLENANORDNUNG UND VERFAHREN ZU DEREN HERSTELLUNG
(EN) ELECTRICALLY PROGRAMMABLE MEMORY CELL ARRANGEMENT AND METHOD FOR THE PRODUCTION THEREOF
(FR) ENSEMBLE CELLULES DE MEMOIRE PROGRAMMABLE ELECTRIQUEMENT ET SON PROCEDE DE PRODUCTION
Abstract
(DE)
Speicherzellen umfassen jeweils einen planaren Transistor. Über einem Kanalgebiet (Ka) ist eine Floating-Gateelektrode (Gf) angeordnet, die einen seitlichen Teil aufweist, der auf einem Rand eines unteren Teils der Floating-Gateelektrode (Gf) angeordnet ist. Der seitliche Teil und der untere Teil der Floating-Gateelektrode (Gf) bilden eine Schicht mit im wesentlichen homogener Dicke, so daß eine horizontale Abmessung des seitlichen Teils im wesentlichen gleich einer vertikalen Abmessung des unteren Teils ist. Eine obere Fläche des unteren Teils der Floating-Gateelektrode (Gf) liegt höher als obere Flächen von Source/Drain-Gebieten. Zur Erzeugung der Speicherzellenanordnung werden die Floating-Gateelektroden (Gf) in ersten Vertiefungen (V1) im Substrat (S) erzeugt. Es werden zweite Vertiefungen (V2) neben den ersten Vertiefungen (V1) erzeugt. An Böden der zweiten Vertiefungen (V2) werden durch Implantation die Source/Drain-Gebiete erzeugt. Die ersten Vertiefungen (V1) und die zweiten Vertiefungen (V2) sind vorzugsweise gleich tief. Vorzugsweise sind in den zweiten Vertiefungen (V2) isolierende Strukturen (I2) angeordnet.
(EN)
The invention relates to memory cells each comprising a planar transistor. A floating gate electrode (Gf) is arranged above a channel region (Ka) and has a lateral part which is arranged on the edge of a lower part of the floating gate electrode (Gf). The lateral part and the lower part of the floating gate electrode (Gf) form a layer with an essentially homogeneous thickness so that a horizontal dimension of the lateral part is essentially equal to a vertical dimension of the lower part. An upper surface of the lower part of the floating gate electrode (Gf) is higher than the upper surfaces of source/drain regions. The floating gate electrodes (Gf) are produced in first cavities (V1) in the substrate (S) in order to produce the memory cell arrangement. In addition to first cavities (V1), second cavities (V2) are produced. The source/drain regions are produced on the bases of the second cavities (V2) by means of implantation. The first cavities (V1) and the second cavities (V2) preferably have the same depth. Insulating structures (I2) are preferably arranged in the second cavities (V2).
(FR)
L'invention concerne un ensemble cellules de mémoire dont chaque cellule de mémoire comprend un transistor planaire. Au-dessus de la zone de canal (Ka) se trouve une électrode de grille flottante (Gf) comportant une partie latérale située sur un bord d'une partie inférieure de l'électrode de grille flottante (Gf). La partie latérale et la partie inférieure de l'électrode de grille flottante (Gf) forment une couche d'épaisseur pratiquement homogène de sorte qu'une dimension horizontale de la partie latérale est pratiquement identique à une dimension verticale de la partie inférieure. Une surface supérieure de la partie inférieure de l'électrode de grille flottante (Gf) est plus élevée que les surfaces supérieures des zones source/drain. Pour fabriquer l'ensemble cellules de mémoire, on génère les électrodes de grille flottante (Gf) dans des premiers creux (V1) du substrat (S), puis on génère d'autres creux (V2) à côté des premiers creux (V1). On crée ensuite les zones source/drain par implantation au fond des deuxièmes creux (V2). De préférence, les premiers creux (V1) et les deuxièmes creux (V2) ont la même profondeur et des structures isolantes (I2) sont placées dans les deuxièmes creux (V2).
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