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1. WO2000041235 - METHOD OF DEPOSITING A COPPER SEED LAYER WHICH PROMOTES IMPROVED FEATURE SURFACE COVERAGE

Publication Number WO/2000/041235
Publication Date 13.07.2000
International Application No. PCT/US1999/030235
International Filing Date 17.12.1999
Chapter 2 Demand Filed 27.07.2000
IPC
H01L 21/285 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/268158
283Deposition of conductive or insulating materials for electrodes
285from a gas or vapour, e.g. condensation
H01L 21/768 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71Manufacture of specific parts of devices defined in group H01L21/7086
768Applying interconnections to be used for carrying current between separate components within a device
H01L 23/532 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
532characterised by the materials
CPC
H01L 21/2855
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
283Deposition of conductive or insulating materials for electrodes ; conducting electric current
285from a gas or vapour, e.g. condensation
28506of conductive layers
28512on semiconductor bodies comprising elements of Group IV of the Periodic System
2855by physical means, e.g. sputtering, evaporation
H01L 21/76877
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76838characterised by the formation and the after-treatment of the conductors
76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
H01L 23/53233
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another ; , i.e. interconnections, e.g. wires, lead frames
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
532characterised by the materials
53204Conductive materials
53209based on metals, e.g. alloys, metal silicides
53228the principal metal being copper
53233Copper alloys
H01L 23/53238
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another ; , i.e. interconnections, e.g. wires, lead frames
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
532characterised by the materials
53204Conductive materials
53209based on metals, e.g. alloys, metal silicides
53228the principal metal being copper
53238Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
H01L 2924/0002
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2924Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
0001Technical content checked by a classifier
0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Applicants
  • APPLIED MATERIALS, INC. [US/US]; P.O. Box 450 A Santa Clara, CA 95052, US
Inventors
  • HASHIM, Imran; US
  • ZHANG, Hong-Mei; US
  • FORSTER, John, C.; US
Agents
  • BERNADICOU, Michael, A. ; Blakely, Sokoloff, Taylor & Zafman LLP 7th floor 12400 Wilshire Boulevard Los Angeles, CA 90025, US
Priority Data
09/226,97708.01.1999US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) METHOD OF DEPOSITING A COPPER SEED LAYER WHICH PROMOTES IMPROVED FEATURE SURFACE COVERAGE
(FR) PROCEDE DE DEPOT D'UNE COUCHE D'ENSEMENCEMENT DE CUIVRE PERMETTANT D'OBTENIR UNE COUVERTURE DE SURFACE AMELIOREE
Abstract
(EN)
We have discovered a method of improving step coverage of a copper seed layer (132) deposited over a semiconductor feature surface (129) which is particularly useful for small size features having a high aspect ratio. Using a contact via (122) as an example of a high aspect ratio feature, we have demonstrated that despite previously-held views, it is possible to increase the copper seed layer coverage simultaneously at the bottom of the via and on the wall of the via by increasing the percentage of the depositing copper species which are ions. The percentage of species ionization which is necessary to obtain sufficient step coverage for the copper seed layer is a function of the aspect ratio of the feature. This increase in the percentage of copper species which are ionized can be achieved using techniques known in the art, such as, for example, laser ablation of the copper target, electron cyclotron resonance, hollow cathode, and applicants' preferred technique, an inductively coupled RF ion metal plasma. We have further discovered that when an inductively coupled plasma is used to increase ionization, an increase in power to the ionization source is not enough to obtain the desired percentage of ions in many cases. It is also necessary to increase the plasma gas pressure. Typically the plasma gas is argon, and the argon pressure in the copper seed layer deposition chamber is increased to fall within the range of about 20 to about 100 mT, preferably between about 30 mT and 70 mT.
(FR)
L'invention concerne un procédé permettant d'améliorer la couverture superficielle d'une couche d'ensemencement de cuivre (132) déposée sur une surface d'éléments semi-conducteurs (129), procédé qui est particulièrement utile pour les éléments de petites tailles présentant un rapport hauteur/largeur élevé. En prenant un trou d'interconnexion (122) comme exemple d'un élément à rapport hauteur/largeur élevé, nous avons montré que, malgré les opinions en vigueur jusqu'ici, il est possible d'augmenter la couverture de la couche d'ensemencement de cuivre simultanément au fond du trou d'interconnexion et sur les parois de celui-ci en augmentant le pourcentage d'espèces de cuivre déposé qui sont des ions. Le pourcentage d'ionisation d'espèces qui est nécessaire pour l'obtention d'une couverture de surface suffisante pour la couche d'ensemencement de cuivre est fonction du rapport hauteur/largeur de l'élément. Cette augmentation du pourcentage des espèces de cuivre qui sont ionisées peut être obtenu grâce à des techniques de l'état antérieur, telles que, par exemple, l'ablation par laser d'une cible de cuivre, la résonance électronique cyclotronique, l'utilisation d'une cathode creuse, et la technique préférée par le déposant, à savoir le dépôt par plasma métallique ionique inductif haute fréquence. Nous avons en outre découvert que lorsque l'on utilise un plasma inductif pour augmenter l'ionisation, une augmentation de courant à la source d'ionisation n'est pas suffisante pour permettre l'obtention du pourcentage désiré d'ions dans de nombreux cas. Il est également nécessaire d'augmenter la pression du gaz de plasma. Normalement le gaz de plasma est de l'argon, et la pression de l'argon dans la chambre de dépôt de la couche d'ensemencement de cuivre est augmentée pour se trouver dans la plage allant d'environ 20 à environ 100 mT, de préférence comprise entre environ 30 mT et 70 mT.
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