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1. WO2000041234 - METHOD AND DEVICE FOR ENCAPSULATING AN ELECTRONIC COMPONENT, NOTABLY A SEMICONDUCTOR CHIP

Publication Number WO/2000/041234
Publication Date 13.07.2000
International Application No. PCT/CH1999/000620
International Filing Date 22.12.1999
Chapter 2 Demand Filed 13.06.2000
IPC
H01L 21/00 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
H01L 21/56 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
56Encapsulations, e.g. encapsulating layers, coatings
H01L 23/31 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
28Encapsulation, e.g. encapsulating layers, coatings
31characterised by the arrangement
CPC
H01L 21/563
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, ; e.g. sealing of a cap to a base of a container
56Encapsulations, e.g. encapsulation layers, coatings
563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
H01L 21/67126
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; ; Apparatus not specifically provided for elsewhere
67005Apparatus not specifically provided for elsewhere
67011Apparatus for manufacture or treatment
67126Apparatus for sealing, encapsulating, glassing, decapsulating or the like
H01L 21/67132
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; ; Apparatus not specifically provided for elsewhere
67005Apparatus not specifically provided for elsewhere
67011Apparatus for manufacture or treatment
67132Apparatus for placing on an insulating substrate, e.g. tape
H01L 2224/32225
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
321Disposition
32151the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
32221the body and the item being stacked
32225the item being non-metallic, e.g. insulating substrate with or without metallisation
H01L 2224/50
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
H01L 2224/73203
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
732Location after the connecting process
73201on the same surface
73203Bump and layer connectors
Applicants
  • ALPHASEM AG [CH/CH]; Andhauserstrasse 64 CH-8572 Berg, CH
Inventors
  • WIRZ, Gustav; CH
  • HERBST, Wolfgang; DE
  • RITZMANN, Heinz; CH
Agents
  • WENGER, René; Hepp, Wenger & Ryffel AG Friedtalweg 5 CH-9500 Wil, CH
Priority Data
99810009.307.01.1999EP
Publication Language German (DE)
Filing Language German (DE)
Designated States
Title
(DE) VERFAHREN UND VORRICHTUNG ZUM VERKAPSELN EINES ELEKTRONISCHEN BAUTEILS, INSBESONDERE EINES HALBLEITERCHIPS
(EN) METHOD AND DEVICE FOR ENCAPSULATING AN ELECTRONIC COMPONENT, NOTABLY A SEMICONDUCTOR CHIP
(FR) PROCEDE ET DISPOSITIF POUR ENCAPSULER UN COMPOSANT ELECTRONIQUE, EN PARTICULIER UNE PUCE DE SEMI-CONDUCTEUR
Abstract
(DE)
Zum Verkapseln eines elektronischen Bauteils, insbesondere eines Halbleiterchips, wird das Bauteil (3) im Abstand auf einen flächigen Träger (2) befestigt. Dazu wird auf dem Träger eine Elastomerschicht (4, 9) aufgebracht, welche die unterschiedlichen Wärmeausdehnungskoeffizienten zwischen Träger und Bauteil ausgleicht. Ein Puffermaterial und/oder ein Klebstoff wird in flüssiger oder pastöser Form aus einem Dispenser aufgetragen und das Bauteil wird bei Raumtemperatur auf das Puffermaterial und/oder den Klebstoff aufgesetzt. Vor dem endgültigen Aushärten wird das Puffermaterial und/oder der Klebstoff zuerst einer Vorhärtung unterzogen. Anschliessend wird das Bauteil mittels elektrischer Leiter mit Kontaktstellen am Träger verbunden und zuletzt erfolgt ein Umhüllen aller verbleibenden Hohlräume inklusive der elektrischen Leiter mit einer Schutzmasse. Das Auftragen des Puffermaterials und/oder des Klebstoffs mit einem Dispenser bewirkt eine erhebliche Rationalisierung.
(EN)
To encapsulate an electronic component, notably a semiconductor chip, the component (3) is fixed to a flat support (2) at a distance therefrom. To this end an elastomer layer (4, 9) is applied to the support which compensates for the different coefficients of thermal expansion between support and component. A buffer material and/or adhesive is applied in liquid or pasty form from a dispenser and the component is placed onto the buffer material and/or the adhesive at room temperature. Before final curing the buffer material and/or adhesive are subjected to precuring. The component is then connected to contact points of the support by means of electric conductors. Lastly all remaining hollow spaces as well as the electric conductors are enveloped by a protective mass. Application of the buffer material and/or adhesive by means of a dispenser constitutes a considerable rationalization.
(FR)
Selon l'invention, pour encapsuler un composant électronique, en particulier une puce de semi-conducteur, on fixe ledit composant (3) sur un support (2) plat, de façon qu'il reste à une certaine distance dudit support. A cet effet on applique sur le support une couche d'élastomère (4, 9) qui compense les différents coefficients de dilatation thermique entre le support et le composant. Un matériau amortisseur et/ou un adhésif sont appliqués, sous forme liquide ou pâteuse, à partir d'un distributeur et le composant est placé, à la température ambiante, sur le matériau amortisseur et/ou l'adhésif. Avant le durcissement définitif, le matériau amortisseur et/ou l'adhésif sont d'abord soumis à un pré-durcissement. Ensuite, le composant est relié, au moyen de conducteurs électriques, avec des points de contact du support et l'on procède à l'enveloppement de toutes les cavités restantes, y compris des conducteurs électriques, avec une matière de protection. L'application du matériau amortisseur et/ou de l'adhésif à l'aide d'un distributeur constitue une rationalisation importante.
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