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1. WO2000041224 - LITHOGRAPHIC METHOD FOR CREATING DAMASCENE METALLIZATION LAYERS

Publication Number WO/2000/041224
Publication Date 13.07.2000
International Application No. PCT/US2000/000235
International Filing Date 06.01.2000
Chapter 2 Demand Filed 26.07.2000
IPC
H01L 21/768 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71Manufacture of specific parts of devices defined in group H01L21/7086
768Applying interconnections to be used for carrying current between separate components within a device
CPC
H01L 21/7688
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76838characterised by the formation and the after-treatment of the conductors
76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
7688by deposition over sacrificial masking layer, e.g. lift-off
H01L 21/76885
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76838characterised by the formation and the after-treatment of the conductors
76885By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
Y10S 438/968
YSECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
10TECHNICAL SUBJECTS COVERED BY FORMER USPC
STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
438Semiconductor device manufacturing: process
968Semiconductor-metal-semiconductor
Applicants
  • LAM RESEARCH CORPORATION [US/US]; P0426 Intellectual Property Law Dept. 4650 Cushing Parkway Fremont, CA 94538-6470, US
Inventors
  • WAGGANER, Eric, D.; US
Agents
  • LEE, Michael; Beyer Weaver & Thomas, LLP P.O. Box 130 Mountain View, CA 94042-0130, US
Priority Data
09/227,22208.01.1999US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) LITHOGRAPHIC METHOD FOR CREATING DAMASCENE METALLIZATION LAYERS
(FR) PROCEDE LITHOGRAPHIQUE DE FABRICATION DE COUCHES DE METALLISATION DAMASQUINEES
Abstract
(EN)
An improved method of forming a metallization layer in a layer stack is disclosed. In one aspect of the invention, a method of performing a lithographic damascene etch on a layer stack to form a metal line is disclosed. The layer stack, which is disposed above a substrate, is comprised of an underlying layer (204). The method of performing the lithographic damascene etch comprises the steps of depositing a photoresist layer (214) above the layer stack and forming a trench (216) in the photoresist layer so that the trench is positioned over the underlying layer of the layer stack. The method continues with depositing a metal layer (220) over the top surface of the photoresist layer and filling the trench, planarizing the metal layer (220) down to about a level of the top surface of the photoresist layer (214) to define a top surface of a metal line, and removing the photoresist layer (214) to leave gaps around the metal line. A dielectric material (226) is then deposited to fill the gaps around the metal line up to a level of about the top surface of the metal line.
(FR)
L'invention concerne un procédé amélioré de fabrication d'une couche de métallisation dans un empilage de couches. Selon un mode de réalisation, l'invention concerne un procédé permettant de réaliser une gravure lithographique par damasquinage sur un empilage de couches de façon à former une ligne métallique. L'empilage de couches, placé au-dessus d'un substrat, comprend une couche sous-jacente. Le procédé de gravure lithographique par damasquinage consiste à déposer une couche de résine photosensible au-dessus de l'empilage de couches, et à former une tranchée dans la couche de résine photosensible de façon que cette tranchée soit placée au-dessus de la couche sous-jacente de l'empilage de couches. Le procédé consiste ensuite à déposer une couche métallique au-dessus de la surface supérieure de la couche de résine photosensible, et à combler la tranchée, à aplanir la couche métallique jusqu'au niveau environ de la surface supérieure de la couche de résine photosensible de façon à définir une surface supérieure d'une ligne métallique, puis à retirer la couche de résine photosensible de façon à laisser des espaces autour de la ligne de métallisation. Un matériau diélectrique est alors déposé afin de combler les espaces autour de la ligne métallique jusqu'au niveau environ de la surface supérieure de cette ligne environ.
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