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1. WO2000041176 - DIGITAL PHASE LOCK LOOP CIRCUIT

Publication Number WO/2000/041176
Publication Date 13.07.2000
International Application No. PCT/JP1999/000055
International Filing Date 08.01.1999
Chapter 2 Demand Filed 31.01.2000
IPC
G11B 20/14 2006.01
GPHYSICS
11INFORMATION STORAGE
BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
20Signal processing not specific to the method of recording or reproducing; Circuits therefor
10Digital recording or reproducing
14using self-clocking codes
H03L 7/07 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7Automatic control of frequency or phase; Synchronisation
06using a reference signal applied to a frequency- or phase-locked loop
07using several loops, e.g. for redundant clock signal generation
CPC
G11B 20/1403
GPHYSICS
11INFORMATION STORAGE
BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
20Signal processing not specific to the method of recording or reproducing; Circuits therefor
10Digital recording or reproducing
14using self-clocking codes
1403characterised by the use of two levels
H03L 7/07
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7Automatic control of frequency or phase; Synchronisation
06using a reference signal applied to a frequency- or phase-locked loop
07using several loops, e.g. for redundant clock signal generation
Applicants
  • FUJITSU LIMITED [JP/JP]; 1-1, Kamikodanaka 4-chome Nakahara-ku Kawasaki-shi Kanagawa 211-8588, JP (AllExceptUS)
  • FUJITSU PERIPHERALS LIMITED [JP/JP]; 35 Saho Yashiro-cho Kato-gun Hyogo 673-1447, JP (AllExceptUS)
  • NANBA, Akira [JP/JP]; JP (UsOnly)
  • OGURA, Kenichi [JP/JP]; JP (UsOnly)
  • OGINO, Manabu [JP/JP]; JP (UsOnly)
Inventors
  • NANBA, Akira; JP
  • OGURA, Kenichi; JP
  • OGINO, Manabu; JP
Agents
  • YOSHIDA, Minoru ; 2-32-1301, Tamatsukuri-motomachi Tennoji-ku Osaka-shi Osaka 543-0014, JP
Priority Data
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) DIGITAL PHASE LOCK LOOP CIRCUIT
(FR) CIRCUIT NUMERIQUE A BOUCLE ASSERVIE
Abstract
(EN)
A digital phase lock loop circuit has a GAC circuit (4) which calculates the average values of the frequencies of the channels in a phase lock state and feeds back the calculation results to a phase lock loop. The GAC circuit has comparators (111 - 118) which compare the frequencies of the channels with an allowable frequency range and, if the frequencies of one or more channels are out of the allowable frequency range, output frequency error signals of the respective channels.
(FR)
Selon cette invention, un circuit numérique à boucle asservie comporte un circuit GAC (4) qui calcule les valeurs moyennes des fréquences des voies dans un état de verrouillage de phase et qui renvoie les résultats du calcul à la boucle asservie. Le circuit GAC comprend des comparateurs (111-118) qui comparent les fréquences des voies avec une plage de fréquences acceptables; si les fréquences d'une ou de plusieurs voies dépassent la plage de fréquences acceptables, il émet des signaux d'erreur de fréquence des voies respectives.
Also published as
Latest bibliographic data on file with the International Bureau