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1. WO2000041070 - A COMPUTER PROCESSOR HAVING A REPLAY UNIT

Publication Number WO/2000/041070
Publication Date 13.07.2000
International Application No. PCT/US1999/029805
International Filing Date 16.12.1999
Chapter 2 Demand Filed 31.07.2000
IPC
G06F 9/38 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
CPC
G06F 9/383
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3824Operand accessing
383Operand prefetching
G06F 9/3838
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3836Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
3838Dependency mechanisms, e.g. register scoreboarding
G06F 9/3842
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3836Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
3842Speculative instruction execution
G06F 9/3851
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3836Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
3851from multiple instruction streams, e.g. multistreaming
G06F 9/3863
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3861Recovery, e.g. branch miss-prediction, exception handling
3863using multiple copies of the architectural state, e.g. shadow registers
G06F 9/3865
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3861Recovery, e.g. branch miss-prediction, exception handling
3865using deferred exception handling, e.g. exception flags
Applicants
  • INTEL CORPORATION [US/US]; 2200 Mission College Boulevard P.O. Box 58119 Santa Clara, CA 95052-8119, US
Inventors
  • MERCHANT, Amit, A.; US
  • SAGER, David, J.; US
Agents
  • HELLER, Paul, H. ; Kenyon & Kenyon Suite 600 333 W. San Carlos Street San Jose, CA 95110, US
Priority Data
09/222,80530.12.1998US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) A COMPUTER PROCESSOR HAVING A REPLAY UNIT
(FR) PROCESSEUR D'ORDINATEUR A MODULE DE REEXECUTION
Abstract
(EN)
A computer processor that has a checker for receiving an instruction. The checker includes a scoreboard, an input for receiving an external replay signal, and decision logic coupled to the scoreboard and the input. The decision logic determines whether the instruction executed correctly based on both the scoreboard and the external replay signal.
(FR)
L'invention concerne un processeur d'ordinateur comportant un vérificateur destiné à recevoir une instruction. Le vérificateur comprend un tableau indicateur, une entrée destinée à recevoir un signal de réexécution externe, et une logique de décision couplée au tableau indicateur et à l'entrée. Cette logique de décision permet de déterminer si l'instruction a été exécutée correctement, en fonction du tableau indicateur et du signal de réexécution externe.
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