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1. WO2000041055 - MATCH LINE CONTROL CIRCUIT FOR CONTENT ADDRESSABLE MEMORY

Publication Number WO/2000/041055
Publication Date 13.07.2000
International Application No. PCT/US2000/000090
International Filing Date 04.01.2000
IPC
G06F 7/02 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
7Methods or arrangements for processing data by operating upon the order or content of the data handled
02Comparing digital values
G11C 15/04 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
15Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
04using semiconductor elements
CPC
G06F 7/02
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
7Methods or arrangements for processing data by operating upon the order or content of the data handled
02Comparing digital values
G11C 15/04
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
15Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
04using semiconductor elements
Applicants
  • NETLOGIC MICROSYSTEMS, INC. [US/US]; 465 Fairchild Drive #101 Mountain View, CA 94043, US
Inventors
  • NATARAJ, Bindiganavale, S.; US
Agents
  • PARADICE, William, L., III; Suite B 511 Linden Street San Francisco, CA 94102, US
Priority Data
09/225,91905.01.1999US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) MATCH LINE CONTROL CIRCUIT FOR CONTENT ADDRESSABLE MEMORY
(FR) CIRCUIT DE COMMANDE A LIGNE D'ADRESSAGE DESTINE A UNE MEMOIRE AUTO-ASSOCIATIVE
Abstract
(EN)
A match line control (ML) circuit includes a weak, static pull-up transistor (32) and a strong, dynamic pull-up transistor (34) coupled between a match line of an associated CAM and a supply voltage (VDD). Prior to compare operations, both the static pull-up transistor and the dynamic pull-up transistor are in a conductive state and thereby quickly charge the match line to the supply voltage. During compare operations, the dynamic transistor is turned off to reduce current flow between the supply voltage and the match line. In some embodiments, the static pull-up transistor and the dynamic pull-up transistor are configured to match the parasitics of the CAM cells (10) coupled to the match line, thereby increasing performance of the associated CAM.
(FR)
Selon cette invention, un circuit de commande à ligne d'adressage comprend un transistor statique faible d'excursion haute et un transistor dynamique fort d'excursion haute couplés entre une ligne d'adressage de la mémoire auto-associative associée et la tension d'alimentation. Avant les opérations de comparaison, le transistor statique faible d'excursion haute et le transistor dynamique fort d'excursion haute sont dans un état conducteur, ce qui leur permet de comparer rapidement les opérations. On éteint ensuite le transistor dynamique pour réduire le flux de courant entre la tension d'alimentation et la ligne d'adressage. Dans certains modes de réalisation, le transistor statique d'excursion haute et le transistor dynamique d'excursion haute sont configurés pour s'adapter aux parasites des cellules (10) de la mémoire auto-associative couplées à la ligne d'adressage, ce qui a pour effet d'améliorer les performances de la mémoire auto-associative associée.
Also published as
Latest bibliographic data on file with the International Bureau