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1. WO2000039928 - HIGH SPEED PIN DRIVER INTEGRATED CIRCUIT ARCHITECTURE FOR COMMERCIAL AUTOMATIC TEST EQUIPMENT APPLICATIONS

Publication Number WO/2000/039928
Publication Date 06.07.2000
International Application No. PCT/US1999/030120
International Filing Date 16.12.1999
IPC
G01R 31/319 2006.01
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28Testing of electronic circuits, e.g. by signal tracer
317Testing of digital circuits
3181Functional testing
319Tester hardware, i.e. output processing circuits
H03K 19/003 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
003Modifications for increasing the reliability
H03K 19/018 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
0175Coupling arrangements; Interface arrangements
018using bipolar transistors only
CPC
G01R 31/31924
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28Testing of electronic circuits, e.g. by signal tracer
317Testing of digital circuits
3181Functional testing
319Tester hardware, i.e. output processing circuit
31917Stimuli generation or application of test patterns to the device under test [DUT]
31924Voltage or current aspects, e.g. driver, receiver
H03K 19/00376
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
003Modifications for increasing the reliability ; for protection
00369Modifications for compensating variations of temperature, supply voltage or other physical parameters
00376in bipolar transistor circuits
H03K 19/01806
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
0175Coupling arrangements; Interface arrangements
018using bipolar transistors only
01806Interface arrangements
H03K 19/01837
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
0175Coupling arrangements; Interface arrangements
018using bipolar transistors only
01837programmable
Applicants
  • RAYTHEON COMPANY [US/US]; 2000 East El Segundo Boulevard P.O. Box 902 El Segundo, CA 90245-0902, US
Inventors
  • LINDER, Lloyd, F.; US
Agents
  • ALKOV, Leonard; Raytheon Company 2000 E. El Segundo Boulevard P.O. Box 902 El Segundo, CA 90245-0902 , US
Priority Data
09/219,75923.12.1998US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) HIGH SPEED PIN DRIVER INTEGRATED CIRCUIT ARCHITECTURE FOR COMMERCIAL AUTOMATIC TEST EQUIPMENT APPLICATIONS
(FR) ARCHITECTURE DE CIRCUIT INTEGRE DE CIRCUIT D'ATTAQUE PIN A HAUTE VITESSE DESTINEE A DES APPLICATIONS D'EQUIPEMENTS D'ESSAI AUTOMATIQUES
Abstract
(EN)
An improved high speed PIN driver integrated circuit and architecture. The architecture of the PIN driver circuit does not rely on transistor clamping during normal operation in active mode, and does not require high reverse base-emitter breakdown voltage in inhibit mode or the active mode, which is in direct opposition to high speed performance at high PIN voltage excursions for CMOS, TTL, ECL level compatibility. In particular, the PIN driver circuit is always an active linear circuit and does always protects the reverse base-emitter voltage of any transistor and does not require wire-OR or clamp transistors. The architecture uses replica biasing to cancel the current of the PIN driver in the inhibit mode, which is a requirement for automatic test equipment where the leakage current produces at the PIN in the inhibit mode is not calibrated out. The replica biasing is implemented using a current mirror circuit, a summing device and a buffer circuit which generates the voltage replica in an active mode of the PIN driver circuit. The replica biasing scheme used in the present invention tracks over temperature and process, and provides for improved high speed circuitry without the need for calibration of leakage currents in the inhibit mode.
(FR)
L'invention concerne un circuit intégré de circuit d'attaque PIN à haute vitesse et une architecture associée améliorés. L'architecture du circuit d'attaque PIN ne s'appuie pas sur le verrouillage de transistor lors du fonctionnement normal en mode actif. Elle ne nécessite pas non plus une tension inverse de claquage d'émetteur élevée en mode inhibé ou actif, ce qui s'oppose directement à la performance à haute vitesse à des excursions de tension PIN élevées pour la compatibilité au niveau CMOS, TTL, ECL. En particulier, le circuit d'attaque PIN est toujours un circuit linéaire actif et ne protège pas toujours la tension inverse d'émetteur des transistors. Il ne nécessite pas non plus des transistors du type OU câblé ou à verrouillage. L'architecture utilise des polarisations de répliques pour annuler le courant du circuit d'attaque PIN en mode inhibé, une exigence pour l'équipement d'essai automatique où le courant de fuite se produit au PIN en mode inhibé n'est pas étalonné. La polarisation des répliques est mise en oeuvre au moyen d'un circuit miroir de courant, d'un dispositif sommateur et d'un circuit tampon qui génère les répliques de tension en mode actif du circuit d'attaque PIN. Le schéma de polarisation des répliques utilisés suit la température et le procédé et permet un circuit à haute vitesse amélioré sans recourir à l'étalonnage des courants de fuite en mode inhibé.
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