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1. WO2000039848 - TEST METHOD AND ASSEMBLY INCLUDING A TEST DIE FOR TESTING A SEMICONDUCTOR PRODUCT DIE

Publication Number WO/2000/039848
Publication Date 06.07.2000
International Application No. PCT/US1999/030916
International Filing Date 22.12.1999
Chapter 2 Demand Filed 07.07.2000
IPC
H01L 23/544 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
544Marks applied to semiconductor devices, e.g. registration marks, test patterns
CPC
H01L 22/34
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
22Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
30Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
34Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
H01L 2924/0002
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2924Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
0001Technical content checked by a classifier
0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
H01L 2924/01005
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2924Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
01Chemical elements
01005Boron [B]
H01L 2924/01006
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2924Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
01Chemical elements
01006Carbon [C]
H01L 2924/14
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2924Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
10Details of semiconductor or other solid state devices to be connected
11Device type
14Integrated circuits
Applicants
  • FORMFACTOR, INC. [US/US]; 5666 La Ribera Street Livermore, CA 94550, US
Inventors
  • ELDRIDGE, Benjamin, N.; US
  • KHANDROS, Igor, Y.; US
  • PEDERSEN, David, V.; US
  • WHITTEN, Ralph, G.; US
Agents
  • LARWOOD, David; Formfactor, Inc. 5666 La Ribera Street Livermore, CA 94550, US
  • MERKADEAU, Stuart, L.; Formfactor, Inc. 5666 La Ribera Street Livermore, CA 94550, US
Priority Data
09/224,16631.12.1998US
09/224,67331.12.1998US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) TEST METHOD AND ASSEMBLY INCLUDING A TEST DIE FOR TESTING A SEMICONDUCTOR PRODUCT DIE
(FR) PROCEDE ET ENSEMBLE DE TEST COMPORTANT UNE MICROPLAQUETTE DE TEST DE MICROPLAQUETTE EQUIPEE
Abstract
(EN)
A test assembly (2000) for testing product circuitry (202, 302, 304) of a product die (2011, 300). In one embodiment, the test assembly includes a test die (2010, 400) and an interconnection substrate (2008) for electrically coupling the test die to a host controller (2002) that communicates with the test die. The test die may be designed according to a design methodology (100) for a test die and a product die that includes the step of concurrently designing test circuitry (202A, 402, 404) and product circuitry in a unified design (102). The test circuitry can be designed to provide a high degree of fault coverage for the corresponding product circuitry generally without regard to the amount of silicon area that will be required by the test circuitry. The design methodology then partitions (104) the unified design into the test die and the product die. The test die includes the test circuitry and the product die includes the product circuitry. The product die may contain some test circuitry. The product and test die may then be fabricated on separate semiconductor wafers. By partitioning the product circuitry and test circuitry into separate die, embedded test circuitry can be either eliminated or minimized on the product die. This will tend to decrease the size of the product die and decrease the cost of manufacturing the product die while maintaining a high degree of test coverage of the product circuits within the product die. The test die can be used to test multiple product die on one or more wafers.
(FR)
La présente invention concerne un ensemble test( 2000) permettant de tester des circuits fabriqués (202, 302, 304) équipant une microplaquette produite (2011, 300). Dans un des modes de réalisation, l'ensemble test comprend une microplaquette de test (2010, 400) et un substrat d'interconnexion (2008) permettant de coupler électriquement la microplaquette de test à un contrôleur hôte (2002) communiquant avec la microplaquette de test. Cette microplaquette de test peut être conçue selon une méthodologie de conception (100) de microplaquette de test et de microplaquette produite, consistant à réaliser simultanément en un seul ensemble (102) des circuits de test (202A, 402, 404) et des circuits produits. En outre, on peut généralement concevoir les circuits de test pour couvrir le plus largement possible les cas de défauts des circuits produits correspondants, sans avoir à prendre en considération la surface de silicium qu'exigeront les circuits de test. La méthodologie de conception consiste ensuite à diviser (104) l'ensemble précité en microplaquette de test et en microplaquette produite. La microplaquette de test comprend le circuit de test, et la microplaquette produite comprend le circuit produit. La microplaquette produite peut comprendre certains circuits de test. Les microplaquettes produites et les microplaquettes de test peuvent alors être fabriquées sur des plaquettes de semi-conducteurs distincts. En séparant les circuits de produit et les circuits de test en puces distinctes, les circuits de test inclus sont soit éliminés, soit ramenés à un minimum dans la puce produite. Ceci permet de réduire à la fois la taille de la microplaquette et son coût de fabrication tout en couvrant le plus largement possible les cas de défauts des circuits produits dans la microplaquette. En outre, on peut utiliser cette microplaquette de test pour tester de multiples microplaquettes produites sur une ou plusieurs plaquettes.
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