Processing

Please wait...

Settings

Settings

1. WO2000039839 - HIGH ASPECT RATIO SUB-MICRON CONTACT ETCH PROCESS IN AN INDUCTIVELY-COUPLED PLASMA PROCESSING SYSTEM

Publication Number WO/2000/039839
Publication Date 06.07.2000
International Application No. PCT/US1999/031075
International Filing Date 28.12.1999
Chapter 2 Demand Filed 26.07.2000
IPC
H01L 21/311 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3105After-treatment
311Etching the insulating layers
H01L 21/768 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71Manufacture of specific parts of devices defined in group H01L21/7086
768Applying interconnections to be used for carrying current between separate components within a device
CPC
H01L 21/31116
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques
3105After-treatment
311Etching the insulating layers ; by chemical or physical means
31105Etching inorganic layers
31111by chemical means
31116by dry-etching
H01L 21/76802
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76801characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
76802by forming openings in dielectrics
Applicants
  • LAM RESEARCH CORPORATION [US/US]; 4650 Cushing Parkway Fremont, CA 94538-6470, US
Inventors
  • MARQUEZ, Linda; US
Agents
  • LEE, Michael; Beyer Weaver & Thomas, LLP P.O. Box 130 Mountain View, CA 94040, US
Priority Data
09/222,55129.12.1998US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) HIGH ASPECT RATIO SUB-MICRON CONTACT ETCH PROCESS IN AN INDUCTIVELY-COUPLED PLASMA PROCESSING SYSTEM
(FR) PROCEDE D'ATTAQUE PAR CONTACT SUB-MICRONIQUE A FACTEUR DE FORME ELEVE DANS UN SYSTEME DE TRAITEMENT AU PLASMA PAR COUPLAGE INDUCTIF
Abstract
(EN)
The invention relates to a method of etching a feature (318) in an oxide layer (314) using a photoresist mask (310), the oxide layer being disposed above an underlying layer (316) of a substrate inside an inductively-coupled plasma processing chamber. The method includes flowing an etchant source gas that includes CH2F2,C4F8 and O2 or C3H3F5,C4F8 and O2 into the plasma processing chamber. The method further includes forming a plasma from the etchant source gas. The method additionally includes etching through the oxide layer (314) of the substrate with the plasma, wherein the etching substantially stops on the underlying layer (316), the underlying being of a silicon layer, a tungsten-based layer or a TiN layer.
(FR)
L'invention concerne un procédé d'attaque d'une caractéristique dans une couche d'oxyde au moyen d'un masque de photorésist, la couche d'oxyde étant disposée au-dessus d'une couche sous-jacente d'un substrat se trouvant à l'intérieur d'une chambre de traitement au plasma par couplage inductif. Le procédé consiste à envoyer un flux de gaz source de réactif d'attaque comprenant CH2F2,C4F8 et O2 ou C3H3F5,C4F8 et O2 dans la chambre de traitement au plasma. Le procédé consiste également à former un plasma à partir du gaz source de réactif d'attaque. Le procédé consiste en outre à effectuer une attaque à travers la couche d'oxyde du substrat avec le plasma, l'attaque s'arrêtant sensiblement à la couche sous-jacente qui consiste en une couche de silicium, une couche à base de tungstène ou une couche de TiN.
Latest bibliographic data on file with the International Bureau