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1. WO2000039821 - IMPROVED LAYOUT TECHNIQUE FOR A MATCHING CAPACITOR ARRAY USING A CONTINUOUS UPPER ELECTRODE

Publication Number WO/2000/039821
Publication Date 06.07.2000
International Application No. PCT/US1999/030528
International Filing Date 20.12.1999
IPC
H01L 27/08 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
08including only semiconductor components of a single kind
CPC
H01L 27/0805
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
08including only semiconductor components of a single kind
0805Capacitors only
Applicants
  • MICROCHIP TECHNOLOGY INCORPORATED [US/US]; 2355 West Chandler Boulevard Chandler, AZ 85224-6199, US
Inventors
  • YACH, Randy, L.; US
  • WOJEWODA, Igor; US
Agents
  • BELL, Catherine, L.; Frohwitter Suite 500 Three Riverway Houston, TX 77056, US
Priority Data
09/221,63423.12.1998US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) IMPROVED LAYOUT TECHNIQUE FOR A MATCHING CAPACITOR ARRAY USING A CONTINUOUS UPPER ELECTRODE
(FR) TECHNIQUE DE MONTAGE AMELIOREE POUR UN ENSEMBLE DE CONDENSATEURS D'ADAPTATION UTILISANT UNE ELECTRODE SUPERIEURE CONTINUE
Abstract
(EN)
A matching capacitor array is implemented on a single, monolithic integrated circuit. The array fastures a matrix of bottom electrodes and a plurality of continuous top electrode strips, where each continuous top electrode strip spans numerous bottom electrodes. The conductive contacts for each continuous top electrode strip are removed from the capacitor interface to the terminal ends of each of the continuous top electrode strips. The invention seeks to match or control parasitic and fringe capacitance, rather than to eliminate or minimize such capacitances. By creating a matched array, the parasitic and fringe capacitances of each matching capacitor unit cell are incorporated into the total capacitance of the unit cell.
(FR)
L'invention concerne un ensemble de condensateurs d'adaptation qui est monté sur un seul circuit intégré monolithe. L'ensemble représente une matrice d'électrodes de fond et plusieurs bandes d'électrodes supérieures continues où chaque bande d'électrodes supérieure continue recouvre les électrodes de fond. Les contacts conducteurs pour chaque bande d'électrodes supérieures continue sont retirés de l'interface de condensateur jusqu'aux extrémités terminales de chacune des bandes d'électrodes supérieures continues. L'invention vise à adapter ou contrôler les capacités parasites et à effets de bords et non pas a éliminer ou supprimer ces capacités. En créant un ensemble adapté, les capacités parasites et à effets de bord de chaque cellule de condensateur d'adaptation sont incorporées dans la capacité totale de la cellule unitaire.
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