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1. WO2000039682 - REGULATING A DATA TRANSFER TIME

Publication Number WO/2000/039682
Publication Date 06.07.2000
International Application No. PCT/US1999/022499
International Filing Date 29.09.1999
Chapter 2 Demand Filed 09.06.2000
IPC
G06F 11/16 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
16Error detection or correction of the data by redundancy in hardware
G06F 13/42 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38Information transfer, e.g. on bus
42Bus transfer protocol, e.g. handshake; Synchronisation
CPC
G06F 11/1679
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
16Error detection or correction of the data by redundancy in hardware
1675Temporal synchronisation or re-synchronisation of redundant processing components
1679at clock signal level
G06F 13/4213
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38Information transfer, e.g. on bus
42Bus transfer protocol, e.g. handshake; Synchronisation
4204on a parallel bus
4208being a system bus, e.g. VME bus, Futurebus, Multibus
4213with asynchronous protocol
Applicants
  • INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, CA 95052, US (AllExceptUS)
  • HOLLAND, Kenneth [US/US]; US (UsOnly)
  • LEE, David [US/US]; US (UsOnly)
  • MEREDITH, Susan [US/US]; US (UsOnly)
Inventors
  • HOLLAND, Kenneth; US
  • LEE, David; US
  • MEREDITH, Susan; US
Agents
  • TROP, Timothy; Trop, Pruner, Hu & Miles, P.C. 8554 Katy Freeway, Ste. 100 Houston, TX 77024, US
Priority Data
09/222,21329.12.1998US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) REGULATING A DATA TRANSFER TIME
(FR) REGLAGE DU TEMPS DE TRANSFERT DE DONNEES
Abstract
(EN)
A computer system (50) includes a bus (52), a first bus device (60), a core circuit (58) and a second circuit (54). The first bus device (60) is coupled to the bus (52) and adapted to furnish a first indication of data to a portion of a bus (52) beginning at a first clock cycle. The bus is capable of skewing the first indication to produce a second indication of the data at another portion of the bus (52) beginning at another clock cycle. The second circuit (54) is coupled to the bus (52) and is adapted to receive an indication of a selected latency time. The second circuit (54) is also adapted to transfer the data to the core circuit (58) in response to the second indication and regulate the transfer so that the circuit receives the data beginning at the selected latency time after the first clock cycle.
(FR)
L'invention concerne un système informatique (50), comprenant un bus (52), un premier dispositif de bus (60), un circuit de base (58) et un second circuit (54). Le premier dispositif de bus (60) est couplé au bus (52), et conçu pour fournir une première indication concernant les données à une partie d'un bus (52), en commençant à un premier cycle d'horloge. Le bus peut induire un décalage de la première indication, de façon à produire une seconde indication concernant les données, pour une autre partie du bus (52), en commençant à un autre cycle d'horloge. Le second circuit (54) est couplé au bus (52), et conçu pour recevoir une indication concernant un temps d'attente choisi. Le second circuit (54) est également conçu pour transférer les données du circuit de base (58), en réponse à la seconde indication, et pour régler le transfert, de façon que le circuit reçoive les données commençant au temps d'attente choisi, après le premier cycle d'horloge.
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