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1. WO2000039670 - DELAYED DEALLOCATION OF AN ARITHMETIC FLAGS REGISTER

Publication Number WO/2000/039670
Publication Date 06.07.2000
International Application No. PCT/US1999/031321
International Filing Date 30.12.1999
Chapter 2 Demand Filed 31.07.2000
IPC
G06F 9/30 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
G06F 9/318 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
318with operation extension or modification
G06F 9/32 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
32Address formation of the next instruction, e.g. by incrementing the instruction counter
CPC
G06F 9/30094
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30094Condition code generation, e.g. Carry, Zero flag
G06F 9/30101
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30098Register arrangements
30101Special purpose registers
G06F 9/3017
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
3017Runtime instruction translation, e.g. macros
G06F 9/30174
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
3017Runtime instruction translation, e.g. macros
30174for non-native instruction set, e.g. Javabyte, legacy code
G06F 9/30196
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30181Instruction operation extension or modification
30196using decoder, e.g. decoder per instruction set, adaptable or programmable decoders
G06F 9/3822
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3818Decoding for concurrent execution
3822Parallel decoding, e.g. parallel decode units
Applicants
  • INTEL CORPORATION [US/US]; 2625 Walsh Avenue Santa Clara, CA 95051, US
Inventors
  • RAMIREZ, Ricardo; US
  • MORRISON, Mike; US
Agents
  • VIKSNINS, Ann, S.; Schwegman, Lundberg, Woessner & Kluth P.O. Box 2938 Minneapolis, MN 55402, US
Priority Data
09/224,62131.12.1998US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) DELAYED DEALLOCATION OF AN ARITHMETIC FLAGS REGISTER
(FR) TEMPORISATION DE LA LIBERATION D'UN REGISTRE A DRAPEAUX ARITHMETIQUES
Abstract
(EN)
A microprocessor capable of delaying the deallocation of an arithmetic flags register is described. A system processes instructions of a first instruction set architecture which has an arithmetic flags register. The system also processes instructions of a second instruction set architecture which is not compatible with the first instruction set architecture. In order to process a first instruction of the first instruction set architecture that implicitly updates the arithmetic flags register, the arithmetic flags register shares a physical destination register with a general register containing a result for the first instruction. An instruction that does not update the arithmetic flags but would deallocate the register containing the arithmetic flags triggers the delayed deallocation mechanism of the present invention.
(FR)
La présente invention concerne un microprocesseur capable de retarder la libération d'un registre à drapeaux arithmétiques. Un système traite les instructions d'une première architecture de jeux d'instructions comportant un registre à drapeaux arithmétiques. Le système traite également les instructions d'une seconde architecture de jeux d'instructions qui n'est pas compatible avec la première architecture de jeux d'instructions. Pour permettre le traitement d'une première instruction de la première architecture de jeux d'instructions qui met à jour implicitement le registre à drapeaux arithmétiques, ce registre à drapeaux arithmétiques partage un registre physique destinataire avec un registre général contenant un résultat destiné à la première instruction. Une instruction qui ne met pas à jour les drapeaux arithmétiques mais qui serait susceptible de libérer le registre contenant les drapeaux arithmétiques déclenche le mécanisme de libération temporisée de la présente invention.
Also published as
GBGB0114445.0
Latest bibliographic data on file with the International Bureau