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1. WO2000039660 - SMART INTEGRATED CIRCUIT

Publication Number WO/2000/039660
Publication Date 06.07.2000
International Application No. PCT/FR1999/003275
International Filing Date 23.12.1999
IPC
G06F 1/00 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/-G06F13/82
G06F 21/55 2013.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
21Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
50Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
55Detecting local intrusion or implementing counter-measures
G06F 21/75 2013.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
21Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
70Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
71to assure secure computing or processing of information
75by inhibiting the analysis of circuitry or operation, e.g. to counteract reverse engineering
G06F 21/77 2013.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
21Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
70Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
71to assure secure computing or processing of information
77in smart cards
G06F 21/81 2013.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
21Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
70Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
81by operating on the power supply, e.g. enabling or disabling power-on, sleep or resume operations
G06F 9/38 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
CPC
G06F 21/755
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
21Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
70Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
71to assure secure computing or processing of information
75by inhibiting the analysis of circuitry or operation
755with measures against power attack
G06F 21/77
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
21Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
70Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
71to assure secure computing or processing of information
77in smart cards
G06F 21/81
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
21Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
70Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
81by operating on the power supply, e.g. enabling or disabling power-on, sleep or resume operations
G06F 2207/7219
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2207Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
72Indexing scheme relating to groups G06F7/72 - G06F7/729
7219Countermeasures against side channel or fault attacks
G06F 9/3879
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3877using a slave processor, e.g. coprocessor
3879for non-native instruction execution, e.g. executing a command; for Java instruction set
G06Q 20/341
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
QDATA PROCESSING SYSTEMS OR METHODS, SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL, SUPERVISORY OR FORECASTING PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL, SUPERVISORY OR FORECASTING PURPOSES, NOT OTHERWISE PROVIDED FOR
20Payment architectures, schemes or protocols
30characterised by the use of specific devices
34using cards, e.g. integrated circuit [IC] cards or magnetic cards
341Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
Applicants
  • BULL CP8 [FR/FR]; 68, route de Versailles Boîte postale 45 F-78430 Louveciennes, FR (AllExceptUS)
  • GRESSUS, Yvon [FR/FR]; FR (UsOnly)
  • SIEGELIN, Christoph [DE/FR]; FR (UsOnly)
  • UGON, Michel [FR/FR]; FR (UsOnly)
Inventors
  • GRESSUS, Yvon; FR
  • SIEGELIN, Christoph; FR
  • UGON, Michel; FR
Agents
  • BULL S.A.; Corlu, Bernard 68, route de Versailles PC58D20 F-78434 Louveciennes Cedex, FR
Priority Data
98/1648528.12.1998FR
Publication Language French (FR)
Filing Language French (FR)
Designated States
Title
(EN) SMART INTEGRATED CIRCUIT
(FR) CIRCUIT INTEGRE INTELLIGENT
Abstract
(EN)
The invention concerns a smart integrated circuit characterised in that it has a main processor (1) and an operating system executing a main programme (P1) to set up a main process performing tasks, at least a secondary processor (2) capable of executing simultaneously at least a secondary programme (P2) to constitute a task-performing process, power circuits (6) common to the processors and means ensuring that the secondary process(es) with similar energy and different operating signature, are carried out simultaneously with the main process by inducing in the power circuits, continuously or intermittently, energy disturbances which are superposed on those of the main process to produce continuous or intermittent data encryption.
(FR)
La présente invention concerne un circuit intégré intelligent. Ce circuit intégré intelligent est caractérisé en ce qu'il possède un processeur principal (1) et un système d'exploitation exécutant un programme principal (P1) pour constituer un processus principal réalisant des tâches, au moins un processeur secondaire (2) capable d'exécuter concurremment au moins un programme secondaire (P2) pour constituer au moins un processus réalisant des tâches, des circuits d'alimentation (6) communs entre les processeurs et des moyens permettant de s'assurer que le ou les processus secondaires d'énergie similaire et de signature de fonctionnement différente, s'effectuent concurremment avec le processus principal en induisant dans les circuits d'alimentation, de façon continue ou intermittente, des perturbations énergétiques qui se superposent à celle du processus principal pour réaliser un brouillage continu ou intermittent.
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