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1. WO2000038241 - EEPROM CELL WITH TUNNELING AT SEPARATE EDGE AND CHANNEL REGIONS

Publication Number WO/2000/038241
Publication Date 29.06.2000
International Application No. PCT/US1999/030058
International Filing Date 16.12.1999
IPC
G11C 16/04 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
04using variable threshold transistors, e.g. FAMOS
H01L 27/115 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
CPC
G11C 16/0441
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
04using variable threshold transistors, e.g. FAMOS
0408comprising cells containing floating gate transistors
0441comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
H01L 27/115
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
Applicants
  • LATTICE SEMICONDUCTOR CORPORATION [US]/[US]
Inventors
  • LI, Xiao-Yu
  • FONG, Steven, J.
Agents
  • FLIESLER, Martin, C.
Priority Data
09/218,98722.12.1998US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) EEPROM CELL WITH TUNNELING AT SEPARATE EDGE AND CHANNEL REGIONS
(FR) CELLULE EEPROM MUNIE D'UNE CANALISATION SUR UN BORD SEPARE ET DE REGIONS DE CANAL
Abstract
(EN)
An EEPROM cell is described that is programmed and erased by electron tunneling at separate regions, an edge of a tunneling drain and a sense transistor channel. The EEPROM cell has three transistors formed in a semiconductor substrate. The three transistors are a tunneling transistor (NMOS), a sense transistor (NMOS) and a read transistor (NMOS). Electron tunneling occurs to program the EEPROM cell through a sense tunnel oxide layer by electron tunneling across an entire portion of a sense channel upon incurrence of a sufficient voltage potential between a floating gate and the sense channel. Electron tunneling also occurs to erase the EEPROM cell through a tunnel oxide layer by electron tunneling at an edge of a tunneling drain upon incurrence of a sufficient voltage potential between the floating gate and the tunneling drain.
(FR)
L'invention concerne une cellule EEPROM qui se programme et s'efface par canalisation électronique sur des régions séparées, un bord d'un drain de canalisation et un canal du transistor de détection. La cellule EEPROM comporte trois transistors formés dans un substrat à semi-conducteur. Les trois transistors sont un transistor de canalisation (NMOS), un transistor de détection (NMOS), et un transistor de lecture (NMOS). La canalisation électronique intervient pour programmer la cellule EEPROM, à travers une couche d'oxyde du canal de détection, par canalisation électronique aux bornes d'une partie entière d'un canal de détection, après application d'une tension suffisante entre une grille flottante et le canal de détection. La canalisation électronique intervient également pour effacer la cellule EEPROM, à travers une couche d'oxyde du canal, par canalisation électronique sur un bord d'un drain de canalisation, après application d'une tension suffisante entre la grille flottante et le drain de canalisation.
Also published as
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