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1. (WO2000036466) SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2000/036466 International Application No.: PCT/JP1998/005619
Publication Date: 22.06.2000 International Filing Date: 11.12.1998
Chapter 2 Demand Filed: 11.12.1998
IPC:
G03F 1/00 (2012.01) ,G06F 17/50 (2006.01) ,H01L 23/528 (2006.01)
G PHYSICS
03
PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
F
PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
1
Originals for photomechanical production of textured or patterned surfaces, e.g. masks, photo-masks or reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
17
Digital computing or data processing equipment or methods, specially adapted for specific functions
50
Computer-aided design
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
528
Layout of the interconnection structure
Applicants:
KOBAYASHI, Kazuhiko [JP/JP]; JP (UsOnly)
MIYAZAKI, Kou [JP/JP]; JP (UsOnly)
HITACHI, LTD. [JP/JP]; 6, Kanda Surugadai 4-chome Chiyoda-ku Tokyo 101-8010, JP (AllExceptUS)
Inventors:
KOBAYASHI, Kazuhiko; JP
MIYAZAKI, Kou; JP
Agent:
TSUTSUI, Yamato; Tsutsui & Associates N.S. Excel 301 22-45, Nishishinjuku 7-chome Shinjuku-ku Tokyo 160-0023, JP
Priority Data:
Title (EN) SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME
(FR) DISPOSITIF A CIRCUIT INTEGRE A SEMICONDUCTEURS ET PROCEDE DE FABRICATION
Abstract:
(EN) A wiring pattern is divided into longer wirings (Ll) and shorter wirings (Ls) depending on a comparison with a reference value, wherein a difference in layout rule between a longer wiring (Ll) and a shorter wiring (Ls) based on a Leviinson phase shift effect provides an interval (S1) between a longer wiring (Ll) and a shorter wiring (Ls) which is relatively smaller than an interval (S2) between longer wirings (Ll).
(FR) L'invention concerne un schéma de câblage divisé en câblages longs (Ll) et courts (Ls), selon la comparaison avec une valeur de référence. Une différence de règle de pose du câblage, entre les câblages longs (Ll) et courts (Ls), qui repose sur l'effet de décalage de phase de Levenson, donne un intervalle (S1) entre câblages longs (Ll) et courts (Ls) relativement inférieur à un intervalle (S2) entre câblages longs.
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Designated States: CN, JP, KR, SG, US
European Patent Office (EPO) (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)