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1. WO2000031871 - IMPROVED FLIP-FLOPS AND OTHER LOGIC CIRCUITS AND TECHNIQUES FOR IMPROVING LAYOUTS OF INTEGRATED CIRCUITS

Publication Number WO/2000/031871
Publication Date 02.06.2000
International Application No. PCT/US1999/026820
International Filing Date 11.11.1999
Chapter 2 Demand Filed 06.06.2000
IPC
H01L 27/02 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H03K 3/3562 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
3Circuits for generating electric pulses; Monostable, bistable or multistable circuits
02Generators characterised by the type of circuit or by the means used for producing pulses
353by the use, as active elements, of field-effect transistors with internal or external positive feedback
356Bistable circuits
3562of the master-slave type
H03K 5/151 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
5Manipulation of pulses not covered by one of the other main groups of this subclass
15Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
151with two complementary outputs
H03K 19/21 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
20characterised by logic function, e.g. AND, OR, NOR, NOT circuits
21EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
H03K 19/23 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
20characterised by logic function, e.g. AND, OR, NOR, NOT circuits
23Majority or minority circuits, i.e. giving output having the state of the majority or the minority of the inputs
CPC
G11C 11/412
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
41forming ; static; cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
412using field-effect transistors only
G11C 8/08
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
8Arrangements for selecting an address in a digital store
08Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
G11C 8/10
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
8Arrangements for selecting an address in a digital store
10Decoders
H01L 27/0207
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
0203Particular design considerations for integrated circuits
0207Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
H01L 27/088
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
08including only semiconductor components of a single kind
085including field-effect components only
088the components being field-effect transistors with insulated gate
H01L 27/092
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
08including only semiconductor components of a single kind
085including field-effect components only
088the components being field-effect transistors with insulated gate
092complementary MIS field-effect transistors
Applicants
  • NANOPOWER, INC. [US]/[US] (AllExceptUS)
  • SCHOBER, Robert, C. [US]/[US] (UsOnly)
Inventors
  • SCHOBER, Robert, C.
Agents
  • MILLIKEN, Darren, J.
  • MALLIE, Michael., J.
Priority Data
60/109,95825.11.1998US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) IMPROVED FLIP-FLOPS AND OTHER LOGIC CIRCUITS AND TECHNIQUES FOR IMPROVING LAYOUTS OF INTEGRATED CIRCUITS
(FR) BASCULES PERFECTIONNEES ET AUTRES CIRCUITS LOGIQUES ET TECHNIQUES POUR PERFECTIONNER LES TRACES DE CIRCUITS INTEGRES
Abstract
(EN)
Techniques for providing improved memory flip-flops and other logic circuits are described. A flip-flop uses only one p-channel transistor (M14) to drive the output node strongly to achieve fast results. To reduce diffusion area, parallel logic is substantially eliminated and only series branches are used, in critical areas. This allows all pull-up transistors and/or all pull-down transistors to be formed from contiguous active areas. The D-to-Q path is reduced, and the clock is used to control the output. The clock becomes the dominant controller of the output when it is located closest to the output. Placing the clock devices (M35, M39-M40) closest to the clocked nodes reduces clock skew. The rising D response time and falling D response time are caused to be as close as possible to reduce the overall cycle time. To reduce parasitics in the circuit, complex-gates are used which are asymmetric. Even multiples of series branches per gate are used to share contacts and eliminate breaks in the layout diffusion. Adding complex-gates to a circuit while using asymmetric gates for smaller layouts achieves additional functionality. One component of the clock, along with the master drive circuit, is used to drive the slave latch of a flip-flop to avoid inserting additional gates into the logic of the fast output path. Reset and set circuitry is designed to be outside the critical path of the clock, and outside the slave latch, to provide rapid Q output response time to the clock and D inputs.
(FR)
La présente invention concerne des techniques de perfectionnement de bascules de mémoire et d'autres circuits logiques. Une bascule utilise un seul transistor à canal P (M14) pour commander avec force le noeud de sortie afin d'obtenir de rapides résultats. Afin de réduire la zone de diffusion, le circuit logique parallèle est sensiblement éliminé et seuls des branchements en série sont utilisés dans des zones critiques. Ceci permet de former tous les transistors d'excursion haute et/ou tous les transistors d'excursion basse à partir de zones actives contigües. Le trajet de D à Q est réduit et on utilise l'horloge pour commander la sortie. L'horloge devient le principal élément de commande de la sortie lorsqu'elle est située le plus près possible de la sortie. En plaçant les dispositifs d'horloge (M35, M39-M40) le plus près possible des noeuds cadencés, on réduit le déphasage des impulsions d'horloge. Le temps de réponse D ascendant et le temps de réponse D descendant sont les plus proches possible afin de réduire le temps de cycle complet. Afin de réduire les parasites dans le circuit, on utilise des portes complexes qui sont asymétriques. On utilise même des multiples de branchements en série par porte afin de partager les contacts et d'éliminer les coupures dans la diffusion du tracé. Le fait d'ajouter des portes complexes à un circuit alors qu'on utilise des portes asymétriques pour des tracés plus petits permet d'obtenir une fonctionnalité additionnelle. Un composant de l'horloge, avec le circuit de commande maître, est utilisé pour commander le verrou esclave d'une bascule afin d'éviter l'insertion de portes supplémentaires dans la logique du trajet de sortie rapide. Un circuit de mise à zéro et de mise à 1est conçu pour être situé en dehors du trajet critique de l'horloge et en dehors du verrou esclave afin de donner un temps de réponse de sortie Q rapide aux entrées D et de l'horloge.
Also published as
US09447499
US09528966
US09649338
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